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Specialized Singulation Punch Design for Package Chip-out Elimination

2019; Linguagem: Inglês

10.9734/jerr/2019/v5i216922

2582-2926

Antonio R. Sumagpang, Frederick Ray I. Gomez,

Manufacturing Process and Optimization

In the semiconductor manufacturing industry, package chip-out is a common defect frequently encountered in trim and form (T/F) process. For thin shrink small outline package (TSSOP), top defect incurred during assembly manufacturing was the package chip-out located at the top surface of the package. In this scenario, the end-of-line (EOL) process parts per million (PPM) and its non-conformance report (NCR) are high. This paper discussed how the TSSOP20 package (hereinafter referred to as Device A) chip-out was addressed and replicated or simulated through package design simulation.