Produção Nacional
Revisado por pares
Single‐phase hybrid discontinuous conduction mode SEPIC rectifiers integrated with ladder‐type switched‐capacitor cells
2019; Institution of Engineering and Technology; Volume: 12; Issue: 11 Linguagem: Inglês
10.1049/iet-pel.2019.0119
ISSN1755-4543
AutoresWilliam de Jesus Kremes, Paulo Júnior Silva Costa, Carlos Henrique Illa Font, Telles Brunelli Lazzarin,
Tópico(s)Silicon Carbide Semiconductor Technologies
ResumoIET Power ElectronicsVolume 12, Issue 11 p. 2832-2842 Research ArticleFree Access Single-phase hybrid discontinuous conduction mode SEPIC rectifiers integrated with ladder-type switched-capacitor cells William de J. Kremes, William de J. Kremes Department of Electrical and Electronic Engineering, Federal University of Santa Catarina, Campus Universitário, s/n, Trindade, Florianópolis, BrazilSearch for more papers by this authorPaulo J.S. Costa, Paulo J.S. Costa orcid.org/0000-0003-2003-1691 Department of Electrical Engineering, Federal University of Technology – Paraná, Av. Alberto Carazzai, 1640 Cornélio Procópio, BrazilSearch for more papers by this authorCarlos H. Illa Font, Corresponding Author Carlos H. Illa Font carlos.illa.font@gmail.com orcid.org/0000-0002-8206-7617 Department of Electronics Engineering, Federal University of Technology – Paraná, Av. Monteiro Lobato, km 04, Ponta Grossa, BrazilSearch for more papers by this authorTelles B. Lazzarin, Telles B. Lazzarin orcid.org/0000-0001-8598-8641 Department of Electrical and Electronic Engineering, Federal University of Santa Catarina, Campus Universitário, s/n, Trindade, Florianópolis, BrazilSearch for more papers by this author William de J. Kremes, William de J. Kremes Department of Electrical and Electronic Engineering, Federal University of Santa Catarina, Campus Universitário, s/n, Trindade, Florianópolis, BrazilSearch for more papers by this authorPaulo J.S. Costa, Paulo J.S. Costa orcid.org/0000-0003-2003-1691 Department of Electrical Engineering, Federal University of Technology – Paraná, Av. Alberto Carazzai, 1640 Cornélio Procópio, BrazilSearch for more papers by this authorCarlos H. Illa Font, Corresponding Author Carlos H. Illa Font carlos.illa.font@gmail.com orcid.org/0000-0002-8206-7617 Department of Electronics Engineering, Federal University of Technology – Paraná, Av. Monteiro Lobato, km 04, Ponta Grossa, BrazilSearch for more papers by this authorTelles B. Lazzarin, Telles B. Lazzarin orcid.org/0000-0001-8598-8641 Department of Electrical and Electronic Engineering, Federal University of Santa Catarina, Campus Universitário, s/n, Trindade, Florianópolis, BrazilSearch for more papers by this author First published: 25 July 2019 https://doi.org/10.1049/iet-pel.2019.0119Citations: 1AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinked InRedditWechat Abstract In this study, a set of new single-phase pulse-width modulation (PWM) Single-ended primary-inductor converter (SEPIC) rectifiers are proposed, which integrates conventional SEPIC rectifier, three-state switch (TSS) and switched-capacitor (SC) concepts. A conventional ladder-type SC cell is modified so that it can be integrated with the SEPIC rectifier operating in discontinuous conduction mode. The set of new single-phase PWM SEPIC rectifiers are able to provide: (i) lower-voltage stress on the semiconductors; (ii) higher-output voltage; and (iii) a split-capacitor output voltage. The structure employs a TSS and three different implementations are proposed. Two of them are bridgeless versions, which can provide higher efficiencies. Hence, the proposed structures can support using the SEPIC rectifiers as step-up in many applications and thus it can broaden its field of use. The topologies and their topological states, a theoretical steady-state analysis, a theoretical analysis of the ladder-type SC cell integrated with the SEPIC rectifier, a dynamic model for the control and a design example are discussed herein. Furthermore, a 500 W prototype with a 220 V input voltage, two 200 V split-output voltages, 400 V total output voltage and 50 kHz switching frequency was designed to corroborate the theoretical study. 1 Introduction Single-phase rectifiers with a high-power factor (PF) have been employed in several types of equipment to meet quality standards set by the market and by the energy industries. In recent years, the energy market has undergone an expressive change with new concepts in relation to distributed generation, smart grids, nanogrids, renewable sources, electrical vehicles and energy storage [1-3]. This new scenario has triggered discussion on new voltage levels, dc current distribution and new equipment. Thus, novel solutions for single-phase pulse-width modulation (PWM) rectifiers will also be needed to adapt the traditional rectifiers for these new scenarios, providing motivation for new research to improve the single-phase rectifiers based on conventional dc–dc converters, for instance, buck, boost, buck-boost, Cúk, SEPIC and Zeta [4, 5]. SEPIC PWM rectifiers can provide a high-PF with less filtering effort (e.g. boost rectifiers) and low-level output voltage (e.g. buck rectifiers). Commonly, SEPIC rectifiers operate in discontinuous conduction mode (DCM), because even without employing a current control, its behaviour is similar to a resistive load to the electrical grid and, thus, the converter drains a current with the same shape as that of the input voltage [6-13]. Although they offer attractive characteristics, one disadvantage of SEPIC rectifier is its voltage stress on semiconductors, which is the input voltage plus the output voltage. This disadvantage causes some limitation in the application as a step-up converter, mainly in output voltage above 400 V. Therefore, novel SEPIC rectifier topologies have been proposed in [14-18] in order to overcome this limitation (they supply higher levels of output voltage with reduced voltage stress on the semiconductors). On the other hand, switched-capacitor converters (SCC) are able to multiply or divide a voltage without increasing the voltage stress across the semiconductors [19-26]. Hence, hybrid structures that integrate a traditional PWM converter and SCC have been applied to increase or to decrease voltages, with lower-voltage stress on semiconductors in relation to the conventional converters. On the basis of the SEPIC rectifier, the multiplier SEPIC dc–dc converter in [19], the SC cell in [20], the hybrid rectifiers in [22], as well as the studies reported in [6-13] and mainly the previous studies presented in [23, 24], this paper proposes a set of hybrid single-phase [SEPIC + SC] rectifiers, in which the SC cell is modified to work with a DCM SEPIC rectifier. Preliminary investigations of these rectifiers were approached in [23, 24]; Costa et al. [23] propose the modified ladder-type SC integrated with SEPIC rectifier and Costa et al. [24] propose the modified ladder-type SC integrated with bridgeless SEPIC rectifiers. This paper generalises the presented studies in [23, 24] in relation to the SEPIC cell, which herein employs a three-state switch (TSS) [27] and three different implementations are proposed, and in relation to SC cell, which herein is generalised for n cells and thus it can provide n gain. This paper also presents a complete theoretical analysis of proposed converters, which are contributions regarding previous publications [23, 24]. The following topics are approached in this paper: generalised topology, operation stages, theoretical waveforms, design equation, analysis of SC cell and how to design it, dynamic model for control, split-capacitor output voltage application and complete experimental verification. It should be noted that [18] extends the voltage-doubler concept to the single-phase SEPIC rectifier, which also provides higher gain with reduced voltage stress. This topology just can double the output voltage in relation to conventional SEPIC and it does not employ SC (uses another concept). It should be also noted that [26] extends the SC concept integrated with SEPIC rectifier presented [23, 24] to the voltage-doubler SEPIC rectifier from [18], which can supply higher gain than [18] with same voltage stress on components. However, these solutions ([18, 26]) employ a great number of components and mainly they are not able to supply split-output voltages naturally, without a voltage balancing control system. Thus, by means of the information previously cited, the authors highlight that the main contribution of this paper is the proposition of a single-phase hybrid DCM SEPIC rectifier, which provides higher gain with reduced voltage stress and has split-output balanced voltages naturally, without a voltage balancing control system. 2 Proposed hybrid SEPIC rectifier The proposed hybrid SEPIC rectifier is shown in Fig. 1, with a generic switching cell of TSS and generic gain provided by SC cells. The elements Li, Ci1, Do1, Lo and Co1 originate from the conventional SEPIC structure. In relation to the generic TSS cell, three different implementations are approached. The first employs one active switch (Fig. 1b) and it is referred to as 1S. The second uses two active switches (Fig. 1c) and it is referred to as 2S. The third employs four active switches (Fig. 1d) and it is referred to as 4S. These cells can be used in applications that require a static gain ≤1 or ≥1 and the versions built with the cells (c) and (d) are bridgeless topologies. Fig. 1Open in figure viewerPowerPoint Proposed hybrid SEPIC rectifier (a) Proposed single-phase hybrid SEPIC rectifier with generic three-state active switching cell and generic SC cell, (b) TSS with one active switch (1S), (c) TSS with two active switches (2S – bridgeless version), (d) TSS with four active switches (4S – bridgeless version) The TSS implementation does not change the main topological stages of the circuit, thus the analysis can be carried out just for one of them. Their differences are related to the current stress on switch components, losses (efficiency) and cost (number of components and gate drivers). The elements CS1, Co2, De1, De2, De3 and Do2 make up the modified SC (MSC) cell. This has two diodes (De1 and Do2) more than the conventional SC (CSC) cell (CS1, De2, De3 and Co2) proposed in [19-22], in order to charge and discharge the SC CS, without changing the voltage across Ci1 from SEPIC stage. Hence, the proposed SC cell maintains the voltage characteristics in Ci1 similar to those of the conventional SEPIC rectifier, and it can reproduce the harmonics of the rectified input voltage to deliver a high-quality input current [10]. After the first multiplier stage, the other SC cells will employ the CSC to increase the gain, as shown in Fig. 1a for CS_n, De_n, De_n+1 and Co_n. SEPIC rectifiers integrated with SC cell able to extend the static gain of SEPIC rectifier and to supply split-output voltages as well. This last feature can be employed to feed loads either with full or with the half value of full voltage. These loads can be balanced or not that even so the SC cells ensure the self-balance of the voltages. If more SCs are added to the structure, more voltage sublevels will be available in the output and thus a different configuration of loads can be used. The split-output voltage is adequate to feed dc–dc or dc–ac half-bridge topologies as the second stage as well. This feature makes these structures attractive for modern applications, which require split-capacitor output voltages. It should be noted that structures based on voltage doubler as [18, 27] not able to offer this option. 2.1 Operation stages The bridgeless version with two active switches (Fig. 1b) was chosen to analyse the concept of the proposed rectifiers; its structure is shown in Fig. 2. The absence of an input diode bridge reduces the number of components and the presence of only one diode and one switch in the current path, during each switching cycle, can result in fewer conduction losses. The rectifier employs two switches, but both employ the same gate driver signal. Fig. 2Open in figure viewerPowerPoint Single-phase hybrid SEPIC rectifier with two active switches (bridgeless version) The rectifier presents eight topological stages for the DCM. The operation stages are seen in Fig. 3 for a positive half period of the grid. The other four topological states are similar; however, a negative voltage at the input must be considered. In steady-state operation, the voltage stresses on Ci1, CS, Co1 and Co2 are, respectively, vg, Vo/2, Vo/2 and Vo/2, where vg is the input voltage and Vo is the average value of the output voltage. Fig. 3Open in figure viewerPowerPoint Operation stages for a positive cycle of voltage grid (a) First stage, (b) Second stage, (c) Third stage, (d) Fourth stage A description of the topological stages is given below and a complete analysis is presented in [23, 24]: First topological stage (Fig. 3a): Switches S1 and S2 are turned on and the diodes De1 and De2 are forward biased. The diodes De3, Do1 and Do2 are reversed biased. Capacitors CS1 and Co1 are parallel connected; however, the charge current of CS1 does not flow through Ci1 due to the MSC cell proposed in this paper. Second topological stage (Fig. 3b): Switches S1 and S2 are turned off. Diodes De3, Do1 and Do2 are forward biased and De1 and De2 are blocked. Capacitors CS and Co2 are parallel connected. Third topological stage (Fig. 3c): This starts when the forward current in Do1 becomes null. In this stage, the capacitor CS and the inductors Li and Lo keep charging Co1 and Co2 and supplying energy to the load. Fourth topological stage (Fig. 3d): The currents ILi_min and ILo_min become equal (with opposite signs). The forward current in diode Do2 is null. This is the traditional discontinuous stage of the SEPIC converter. 2.2 Main ideal waveforms The main ideal waveforms of the proposed converter are illustrated in Fig. 4 for a grid period and Fig. 5 for a switching period. The waveforms are typical waveforms from an ideal converter and operating in DCM. Fig. 4Open in figure viewerPowerPoint Ideal waveforms in one grid period Fig. 5Open in figure viewerPowerPoint Ideal waveforms for the switching period The input voltage (vg), input current (iLi), current in the inductor (iLo), output voltage (Vo) and voltage on capacitors Ci1, Co1, Co2 and CS (VCi1, VCo1, VCo2 and VCS) are shown in Fig. 4 for one cycle of the voltage grid. The input current is in phase with the input voltage and it ensures the multiplication of the output voltage (VCo1 = VCo2 and Vo = 2VCo1). The currents in the inductors Li and Lo, the currents in the capacitors Ci1 and CS, the currents in the switches S1 and S2, the currents in the output diodes Do1 and Do2, the voltage across the inductors Li and Lo, the voltages across switches S1 and S2 and the voltages across the output diodes Do1 and Do2 are shown in Fig. 5 for one switching period. 3 Theoretical analysis The main design equations for the power converter are described as follows. 3.1 Static gain, maximal duty cycle and critical resistance The output current average value of the rectifier in DCM is defined by (1), which can also be described by (2) (1) (2)The static gain (M) of the proposed converter is defined by the ratio between the output voltage (Vo) and the input voltage peak (VP). In DCM, substituting (2) into (1), M is determined by (3), where Leq is given by (4) (3) (4)On the other hand, the static gain of the proposed converter in CCM is the conventional CCM SEPIC gain and it is herein rewritten by the equation below: (5)Hence, the boundaries between CCM and DCM are given by (6) and the critical resistance value that ensures the DCM operation is defined by (7). Equations (6) and (7) delimit, respectively, the values of the maximal duty cycle and critical resistance, which will ensure the DCM operation (details about these equations are found in [28]) (6) (7)The curves of static gain in relation to the duty cycle of the proposed converter in DCM are depicted in Fig. 6. The auxiliary variable kx in Fig. 6 is describes by the equation below: (8) Fig. 6Open in figure viewerPowerPoint Static gain curves in relation to the duty cycle of the proposed rectifier in DCM 3.2 Inductors design The values of Li and Lo are determined by (9) and (10), respectively. Vp is the peak value of the input voltage; Vo is the average value of the output voltage; ΔiLi is the ripple current in inductor Li; Ro is the equivalent load resistance; fs is the switching frequency; and D is the duty cycle (9) (10)The root-mean-square (RMS) current values of the input and output inductors are given by the equations below: (11) (12) 3.3 Capacitors design The capacitance values for Ci1, Co1 and Co2 are given by (13) and (14). Po is the output power and thold is the hold-up time [29]. The capacitor Ci1 is designed from a high-frequency ripple voltage specification and capacitors Co1 and Co2 are designed from a hold-up-time specification (13) (14)The RMS current values of capacitors Ci1, Co1 and Co2 are defined, respectively, by the equations below: (15) (16) (17) 3.4 Semiconductor design The maximum voltage values across switches S1 and S2 are determined by the equation below: (18)The RMS values of the currents of switches S1 and S2 are given by (19), where ICS1_max is the maximum current in CS1 (19) The maximum voltage values across diodes Do1 and Do2 are defined by the equations below, respectively: (20) (21)The average values of the currents of diodes Do1 and Do2 are given by the equation below: (22) 3.5 SC cell design The SC cell from the proposed rectifier is highlighted in Fig. 7a. Its simplified electrical circuit is shown in Fig. 7b and its equivalent circuit in Fig. 7c, which is a resistance that simulates its conduction losses. The resistance Req is given by (23) being τ presented in (24) (23) (24) Fig. 7Open in figure viewerPowerPoint SC cell (a) SC cell integrated with SEPIC rectifier, (b) Equivalent circuit of the SC cell employed in the proposed rectifier, (c) Equivalent resistance of the SC cell The resistance Ron−c (Fig. 7) is the total conduction resistance of the SC, which represents the conduction resistance of semiconductors (Ron) plus the capacitor resistances (Rce). The variable fs is the switching frequency, τ is the time constant [defined in (25)] and CS is the SC. The Req in relation to fsτ (to one fixed duty cycle) is shown in Fig. 8, which shows the three operation modes of SC. The value of fsτ = 0.5 is proposed as operation point for the SC cell (this point represents an equivalent resistance of 1.08 pu regarding the minimal resistance when fsτ tends to infinity) [28]. Thus, this value is used in the design of the SC cell. Fig. 8Open in figure viewerPowerPoint SC cell: Req as a function of fsτ The capacitance of SC is described as the equation below: (25)Using fsτ = 0.5 and D = 0.35 (which ensures the DCM operation) in (25), the value for the SC is obtained by the equation below: (26)At this operation point, the current RMS value for capacitor CS is defined as (27), where ICS_max is the maximum current in CS and ICS_min is the minimum current in CS (27) 3.6 Generalisation of SC cell number The static gain of the proposed rectifier can be generalised by adding SC cells, in a modular solution, as shown in Fig. 1. Therefore, the component count in the multiplication stage and the average value of the output voltage are directly proportional to the number of SC cells employed. Therefore, for a generalised number of SC cells (n), the number of diodes and capacitors employed is defined by (28) and (29) and the output voltage provided by (30) (28) (29) (30)It should be highlighted that the voltage stresses on the diodes, metal–oxide–semiconductor field-effect transistors and capacitors will remain constant, as defined by the equations below: (31) (32) (33) (34) (35) 4 Control-oriented modelling 4.1 Control-oriented model On the basis of [10, 30], the input current of DCM SEPIC rectifiers does not have to be controlled and, thus, the set of proposed rectifiers only require an output voltage control, which is exemplified in Fig. 9. A simplified model can be used to study the dynamic model for the output voltage in relation to the duty cycle of the proposed topology, which is illustrated in Fig. 10. Fig. 9Open in figure viewerPowerPoint Block diagram for the output voltage control Fig. 10Open in figure viewerPowerPoint Equivalent circuit of the proposed rectifier The value of the current io is defined by (36) and it is modified when the duty cycle or output voltage is changed (36)When d is changed, vo will also change. Therefore, there is a correlation between the variables io, d and vo, which must be considered in the dynamic model. Hence, the output current is a function that can be described as (37), where Co_eq is described by (38) (37) (38)A disturbance in the duty cycle (d) causes a variation in the current io composed of direct variation and indirect variation. Thus, the current variation, arising from a duty cycle variation, can be given in partial functions as in the equation below: (39)Applying (36) into (39) and affecting the needed mathematical operations give the equation below: (40)Substituting (37) into (40) results in the equation below: (41)Applying the Laplace transform in (41), which is manipulated in order to obtain the output voltage variation, according to the variation in the duty cycle is shown in (42). This equation is the transfer function of the converter model for average values of small signal (42) 4.2 Validation of the control-oriented model The small-signal model for control was validated by numerical simulation. Tables 1 and 2 show the specifications. Table 1. Design specifications Specification Value input voltage 220 V output voltage 400 V output power 500 W switching frequency 50 kHz maximum duty cycle 0.35 hold-up time 16.667 ms capacitor Ci1 ripple 20% inductor Li ripple 10% Table 2. List of components Component Specification inductor Li inductance: 6.77 mH turns: 220 wire: 18 AWG core: APH46P60 inductor Lo inductance: 120.6 μH turns: 29 wire: 64 × 32 AWG core: EE42/20 3c94 transistors S1 and S2 IPZ65R019C7 (700 V/19 mΩ) diodes Do1 and Do2 MUR1560 (600 V/15 A) diodes De1, De2 and De3 MUR860 (600 V/8 A) diodes D1 and D2 1N5408 (1000 V/3 A) capacitor Ci1 2 × 470 nF/400 V capacitors Co1 and Co2 2 × 1.5 mF/250 V capacitor CS 2 × 1.5 mF/250 V control circuit UC3525A During the test, a decrement of 1.4% is added to the duty cycle at t = 2.3 s and after 1.3 s the value returns to the initial value. The behaviour of the output voltage in the converter and the proposed converter model can be seen in Fig. 11. Fig. 11Open in figure viewerPowerPoint Validation of a dynamic model for control: steady-state and transient-state behaviours of vo and vmod 5 Experimental evaluation 5.1 Verification of the proposed rectifier The concept of the proposed rectifiers was verified in two 500 W prototypes. One used the TSS with two active switches (2S – Fig. 1c) and the following waveforms are related to that structure. In the other prototype, one active switch (1S – Fig. 1b) was employed, and only its efficiency, PF and total harmonic distortion (THD) will be discussed in this paper. All results reported herein were obtained with the rectifiers operating in rated power (500 W) and in closed loop. The prototype specifications are given in Table 1 and a list of the components can be seen in Table 2. A photograph of the 2S prototype, which has a specific power of 0.339 kW/kg and power density of 0.277 kW/l, can be seen in Fig. 12. Fig. 12Open in figure viewerPowerPoint Photograph of the prototype The integrated circuit UC3525A was used to implement the control and PWM circuits. A controller proportional–integral plus low-pass filter was chosen to control the rectifier. Its transfer function is defined in (43) and its design data are seen in Table 3 (43) Table 3. Data of controller design Specification Value zero z1 1 Hz pole p1 0 Hz pole p2 5 kHz gain ki 1 × 109 sensor gain 0.013 PWM gain 0.286 To verify the robustness of the controller, the output power was changed from 10 to 150% of rated power and the capacitances and inductances from 90 to 110% of nominal value (parametric variation of ±10%). During the analysis, the frequency behaviour of the compensated transfer function was checked. Fig. 13 shows the Bode diagram considering nominal conditions to Po, Co1, Co2, Ci1, Li and Lo. In addition, the shaded area defines the boundary of the Bode plot regarding the limit values of parametric variation tested in these variables. It should be observed that the crossover frequency and phase margin remains unchanged at 100 Hz and 90°. A small variation between −80° and −120° can be noted in the phase margin for low frequencies around 1 Hz; however, this does not unstable the system. Fig. 13Open in figure viewerPowerPoint Bode diagram considering parametric variations: from 10 to 150% of rated power and from 90 to 110% of the nominal values of capacitances and inductances It should be noted that only conventional methodologies of modelling and control were applied herein because the main focus of this paper is the steady-state analysis of the proposed topology. Thus, the controller was designed and verified only for constant voltage load. However, as has been happening with boost rectifier, there is a big field regarding control strategies and loads, which can be approached for this topology as well. Experimental waveforms of the input voltage (vg) and the inputcurrent (iLi) are presented in Fig. 14 at the rated power (500 W). The resultsshow that the input current has a sinusoidal waveform and it is in phase withthe input voltage. The harmonic spectrum for the input current is shown inFig. 15, with a THD of around 2.3531%,leading to a converter PF of 0.9986. Fig. 14Open in figure viewerPowerPoint Input voltage (100 V/div) and input current(3 A/div) Fig. 15Open in figure viewerPowerPoint Input current harmonic spectrum (brown colour) andIEC61000-3-2 limits (grey colour) The waveforms of the output voltage and output current are seen in Fig. 16, with average values of 400.3 V and 1.28 A,respectively. The output power measured in this case was ∼512.38 W. Fig. 16Open in figure viewerPowerPoint Output voltage (50 V/div) and current (500 mA/div)waveforms The voltages across CS1, Co1 andCo2 are shown in Fig. 17. They are balanced and they have values of around 200 V.This feature ensures a voltage multiplication, i.e. a rectifier with doublestatic gain. The output voltage was about 400 V. Fig. 17Open in figure viewerPowerPoint Output voltage (100 V/div) and the voltage across capacitorsCo1 and Co2 (50 V/div) Fig. 18 shows the current and ripple voltage waveforms inthe SC CS1. The peak and RMS values of the currentwere 9.55 and 3.79 A, respectively. The current shape demonstrates the partialcharge mode of the SC circuit. Fig. 18Open in figure viewerPowerPoint Current through CS1 (5 A/div) and ripple voltageacross CS (3 V/div) Fig. 19 shows the voltage on the semiconductors S1, S2 and Do1. The maximum values of the voltage on these elements were 534, 523 and 554 V, respectively. In the proposed hybrid rectifier, the theoretical maximum voltage across the semiconductors is the sum of the peak input voltage and half of the output voltage, i.e. 511 V for the design specifications. To a conventional SEPIC rectifier, this effort is the sum of the peak value of the input voltage and the output voltage and will be 711 V. Fig. 19Open in figure viewerPowerPoint Voltage across the switches and diode Do1 (200 V/div) The dynamic response of the rectifier to a load step of + 50% (from 50 to 100% of the rated power) is shown in Fig. 20. The output voltage presented overshoot and settling time of 1.16% and 400 ms, respectively. Fig. 20Open in figure viewerPowerPoint Dynamic response of the proposed rectifier (vo – 50 V/div; iRo – 1 A/div; iLi – 3 A/div) to a load step of + 50% The experimental curves relative to efficiency, THD and PF of the proposed converter [for the commutation cells (b) and (c)] with n equal to 1 are shown in Figs. 21–23. Fig. 21Open in figure viewerPowerPoint Curves of efficiency of the proposed converters Fig. 22Open in figure viewerPowerPoint Measured THD of the proposed converters Fig. 23Open in figure viewerPowerPoint Measured PF of the proposed converters Both implementations (1S and 2S) present similar results, reaching around 94.3% efficiency at rated power. The efficiency at the rated power is ∼94.53 and 94.28%. It should be noted that the rectifiers work in DCM, with no current control and without any soft commutation technique. The THD and PF are shown in Figs. 22 and 23. The THDs are 3.37 and 2.35% and the PFs are 0.9943 and 0.9986. 5.2 Results of the hybrid SEPIC rectifier with split-capacitor output The proposed rectifier was tested under split-balanced and unbalanced loads. First was verified under split-balanced load [Ro1 = 151 Ω (265 W) and Ro2 = 151 Ω (265 W)]. The output voltage and the voltage across capacitors Co1 and Co2 are shown in Fig. 24. The
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