Design of integer‐ N PLL frequency synthesiser for E‐band frequency for high phase noise performance in 5G communication systems
2019; Volume: 9; Issue: 1 Linguagem: Inglês
10.1049/iet-net.2018.5245
ISSN2047-4962
AutoresZakia Berber, Samir Kameche, Elhadj Benkhelifa,
Tópico(s)Microwave Engineering and Waveguides
ResumoIET NetworksVolume 9, Issue 1 p. 23-28 Research ArticleFree Access Design of integer-N PLL frequency synthesiser for E-band frequency for high phase noise performance in 5G communication systems Zakia Berber, Corresponding Author Zakia Berber zakia.berber@gmail.com Department of Telecommunications, STIC Laboratory, University of Technology, Tlemcen, AlgeriaSearch for more papers by this authorSamir Kameche, Samir Kameche Department of Telecommunications, STIC Laboratory, University of Technology, Tlemcen, AlgeriaSearch for more papers by this authorElhadj Benkhelifa, Elhadj Benkhelifa School of Computing and Digital Technologies, Staffordshire University, Stoke on Trent, ST4 2D UKSearch for more papers by this author Zakia Berber, Corresponding Author Zakia Berber zakia.berber@gmail.com Department of Telecommunications, STIC Laboratory, University of Technology, Tlemcen, AlgeriaSearch for more papers by this authorSamir Kameche, Samir Kameche Department of Telecommunications, STIC Laboratory, University of Technology, Tlemcen, AlgeriaSearch for more papers by this authorElhadj Benkhelifa, Elhadj Benkhelifa School of Computing and Digital Technologies, Staffordshire University, Stoke on Trent, ST4 2D UKSearch for more papers by this author First published: 01 January 2020 https://doi.org/10.1049/iet-net.2018.5245Citations: 2AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract A phase-locked loop (PLL) frequency synthesiser is designed for 5G E-band frequency. ADF4155-PLL chip with an external (loop filter, prescaler, VCO and an external reference oscillator) is simulated using the ADIsimPLL tool. With a third-order passive filter having 1 MHz loop bandwidth and 45° phase margin, simulation results show that the proposed synthesiser achieves a total phase noise (PN) of −81.50 and −115.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for (71–76 GHz) and −80.39 and −114.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for the highest (81–86 GHz) 5G frequency range even if −160 dBc/Hz VCO noise floor and −170dBc/Hz reference PN floor are integrated in the design. Also, the performance of the system in terms of RMS jitter and reference spurs are verified. The proposed synthesiser for 5G application presents very low reference spurs (−113, −112 dBc) at 50 MHz offset frequency and low RMS jitter (0.39, 0.40 ps) for 70 and 80 GHz frequency band, respectively. 1 Introduction The standardisation process of 5G began in 2014 and is planned to be completed by 2020. The future generation will represent the prospect of a better digital world. Many devices will be connected to the internet, ranging from power supply systems and medical equipment, to the traffic lights, household appliances and cars (implementation and integration of IoT (Internet of Things), D2D 'Device-to-Device' and M2M 'Machine-to-Machine' technologies) [1]. To provide the capacity to support this wide variety of services, 5G network faces a set of challenges: 20 Gbit/s peak data rate, 100–1000 Mbit/s user experienced data rate (1000 Mbit/s in hotspot and 100 Mbit/s anywhere), a minimum time delay of 1 ms (for low latency services); up to 500 km/h high speed availability; a maximum 1 million connections per km2 (for massive connections); hundred times of energy consumption compared with current systems (mainly for IoT); and a maximum up to 5 times spectrum efficiency increase of current systems [2]. Moreover, according to the well-known Shannon's theory, the advantage to use higher frequencies allow for larger bandwidth allocations which translate directly to higher data transfer rates. That is why, 5G networks plan to leverage several new spectrums especially mm-Wave (mmW) spectrum which can be deployed at frequencies from 20 to 90 GHz [3, 4]. However, most of the researches nowadays are explored for Ka (27–40 GHz) band frequency. Recently, data rate of more than 0.5 Gb/s has been achieved over a few hundred metres of radius for outdoor/indoor coverage using 28 GHz band with 800 MHz bandwidth [5, 6]. Otherwise, higher frequencies can demonstrate better data rate by using larger bandwidths. According to Nokia [3], 1 GHz up to 2 GHz of total aggregated bandwidth can be used for frequencies above 20 GHz. So, the main contribution of this paper consists of the use of the highest 5G-mmW band frequency. It targets E-band (71–76 GHz), (81–86 GHz) having 1 GHz ultra-wideband (bandwidth) communication channel. In addition, 5G wireless systems such as the transceivers will need high performance component with minimal noise characteristics, low spur signals and high stability. Indirect frequency synthesis known as phase-locked loop (PLL) frequency synthesiser, is a significant part of any communication system which allows the generation of a wide range of output frequencies. For 5G applications, this device must be able to generate frequency bands required by 5G networks. Many investigations reported in [6-11] demonstrate a good performance of PLL synthesisers for K-band and several architectures are proposed to improve PLL characteristics including phase noise (PN), reference spurs and RMS jitter. So, the second goal of this work is by using ADF chip from analogue devices company, more precisely 'ADF4155', we would like to demonstrate that the design of an integer PLL synthesiser for E-band frequency can perform as well as those studied so far. The paper is organised as follows: Section 2 presents the background and motivation of the work. Section 3 deals with the data used for the design and simulation of the PLL system. Simulation results of the proposed circuit for E-band frequency with a comparison of state-of-the-art mmW frequency synthesisers are also analysed in this Section. Conclusion is drawn in Section 4 and finally the references cited in this work are set out in Section 5. 2 Background and motivation The simulation of the proposed system is done using ADIsimPLL tool. This software makes it easy to design, analyse and simulate the frequency synthesiser systems. Several versions are available online and each one offers a large selection of 'ADFxxxx' PLL chip. Some authors have used 'ADF4350' in their investigations to design an Ultra-broadband Microwave Sources [12] or even to combine it with several type of filters to improve the performance of the PLL system [13]. Other research by Liang [14] based on the programmable frequency dividers HMC394 in conjunction with integer PLL chip 'ADF4107', had been proposed also to improve the PN criterion. Moreover, the large choice of ADF series allows its adaptation in different fields of application. Authors of [15, 16] have proposed a design of S-band frequency synthesiser for microwave application by integrating ADF4350/1 and ADF4113 PLL chip, while Gramarchuk et al. [17] have developed a model based on 'ADF41020' for the radar system which can include also devices for the mmW range. The idea to use ADF41020 for mmW applications has prompted us to adapt it to synthesiser systems for E-band frequency, but unfortunately, this chip is limited by its frequency range which makes the simulation on ADIsimPLL impossible. By the way, ADF4155 PLL chip, has been used for many applications like Wireless LANs, CATV equipment, Clock generation but also it has been widely employed in wireless infrastructure (W-CDMA, WiMAX, GSM, DCS, …) [18]. So, in this paper, by using the ADIsimPLL software package version 4.30.03 [19], we would like to adapt ADF4155-chip to 5G synthesiser systems. As illustrated in Fig. 1, the general concept of PLL chip contains a phase frequency detector (PFD), a charge pump (CP) and a frequency divider (R and N). The PFD is used to detect the phase difference between the input reference signal (Fref) which comes from the TCXO oscillator (divided by a factor R) and the feedback signal (Fout / N), then produces Up/ Down signal to the CP which converts its pulse width into the current (ICP). The loop filter is placed outside the chip it suppresses the high-frequency components of the CP output allowing the dc (Vtune) value to control the VCO frequency (Fout). The output frequency (Fout) of VCO feedbacks to the PFD through the frequency divider (1/ N) [20]. When the loop is in a locked condition, the relationship between the input and output frequencies can be expressed as (1) Fig. 1Open in figure viewerPowerPoint Integer PLL frequency synthesiser 2.1 Phase frequency detector/charge pump PFD plays an important role in the PLL system. It is the element which converts the phase difference applied to its input into an output voltage. Fig. 2 shows a schematic diagram of the conventional PFD of ADF-4155. It consists of two D-Flip Flops (U1 and U2), an AND gate (U3) and a delay element (U4). Fout /N and Fref coming from N and R counters, respectively, are applied at U1 and U2 and combined by AND gate (U3). A delay (U4) of 2.60 ns is inserted in the reset path to ensure that there is no dead zone effect in the PFD. In ADF 4155 PLL chip, PFD and CP are assembled in one block. CP component allows converting PFD output voltage to a current (ICP) which offers the advantage to produce an infinite pull in range and zero steady state phase error [21]. However, CP suffers from leakage current (Ileak). This undesirable current depends on the CP output current at simultaneously open transistor switches (T1) and (T2). In some applications, high leakage current can have an impact on overall system performance. In ADIsimPLL, leakage current is limited at one tenth of CP current (ILeakage < ICP) and influences directly on reference spur characteristic. Fig. 2Open in figure viewerPowerPoint Bloc diagram of PFD/CP 2.2 N feedback divider Fractional or integer PLL for frequency synthesis depends only on the programmable N frequency divider, known also as a counter (N). Researchers who conducted their work in the study of frequency synthesis in K-band for 5G applications, turned their attention to the exploration of new design of fractional-N frequency synthesisers while the integer ones offer a much lower level of complexity whereas maintaining good performance of systems. In this work, we adopt the integer-N PLL synthesiser architecture for E-band 5G wireless systems. The implementation of N division ratio of ADF4155 allows both of two modes (integer/fractional). It uses a programmable dual-modulus prescaler of 4/5 or 8/9 determining by the INT, FRAC1, MOD1, FRAC2 and MOD2 values. It is expressed in (2) and shown in Fig. 3. However, in the integer architecture, N divider takes only integer values and the reference frequency equals the frequency of channel spacing. Moreover, it can be changed to produce a range of VCO frequencies that have the same frequency accuracy of PFD which means that the output frequency changes by only integer multiples of Fref [22]. On the other hand, ADF4155 allows an input PFD frequency up to 125 MHz while 1 up to 2 GHz of bandwidth channel is required for frequencies above 20 GHz. So, to solve this problem, an external prescaler (P) is added in the synthesiser circuit to have 1 GHz channel spacing for E-band frequency (this is more clear in the next Section 3). (2)where INT is the integer value, FRAC1 is the numerator of the primary modulus, FRAC2 is the numerator of the auxiliary modulus, MOD2 is programmable of the auxiliary fractional modulus and MOD1 is a primary modulus with a fixed value. Fig. 3Open in figure viewerPowerPoint N frequency divider with dual-modulus prescaler 2.3 Phase noise PN characteristic affects significantly the quality of the RF transceivers. An important PN can damage the performance of the system. For that, it must be carefully taken into consideration. Generally, it is characterised in the frequency domain. To analyse its effect, it is better to use the linear model. As shown in Fig. 4, in PLL synthesiser, each block constituting the circuit, is affected by a noise source assigned to it. Fig. 4Open in figure viewerPowerPoint PLL PN contributors When the PN floor of PFD, the comparison frequency and N of the divider are considered together, the PLL flat noise can be modelled in the following equation[7, 16]: (3)Equation (3) is available only to calculate the PN within the loop bandwidth. Outside the loop bandwidth, the PN is multiplied by the closed-loop transfer function [16]. So, the total output PN reported in [23] can be expressed by the general equation (4), while the transfer function of the closed-loop reported by [24] may be described by (5). (4)where PNTot2 is the total PN power at the output, X2 is the noise power at the output due to PNN and PNRef, Y2 is the noise power at the output due to PNCP and Z2 is the noise power at the output due to PNVCO(5)where G (s) is the forward loop gain and it is given by (6)Kφ and KVCO are the transfer function of the CP and VCO, respectively. Z (s) is the transfer function of the loop filter. In this paper, a third-order loop filter is used. Its transfer function is given by the following equation (7) [25]: (7)and (8)H (s) is the reverse loop gain and it is expressed by (9)Therefore, (4) becomes (10) (11) (12) 3 Design and simulation 3.1 Design of PLL synthesiser for E-band frequency To recall, the aim of this work is to design an integer frequency synthesiser which generates and controls a very stable signal with low noise, low spurs and low RMS jitter for E-band 5G communication systems. By simulating ADF4155 PLL chip on ADISimPLL 4.30.03 software, the specified parameter values of the synthesiser to generate both (71–76 GHz) and (81–86 GHz) frequency bands are: The reference frequency (Fo) which comes from the crystal oscillator is 250 MHz. The input PFD frequency (Fref) is 50 MHz. The factor R resulting from the relation (R = Fo / Fref) is 5. The external prescaler (p) is divided by 20 to select 1 GHz channel spacing (50 MHz × 20). 1 nA leakage current is introduced in the CP phase detector with Icp magnitude of 938 μA. The VCO gain (Kvco) is 2.00 GHz/V. The divider (N) is programmed in integer mode. According to (1), N = (1620–1720). The third-order passive loop filter is designed with 45° phase margin and 1 MHz loop bandwidth. According to [24, 26], these parameter values are considered as optimal to design PLL synthesiser for E-band frequency. The PN oscillators using the broadband floor and corner frequency is specified in both of the TCXO and VCO. o For the reference PN: it is specified with −170 dBc/Hz PN Floor (PNFloor), 10 kHz corner frequency and 10 Hz flicker corner. o For the VCO PN: it is specified with −160 dBc/Hz floor, 100 kHz corner frequency and 10 Hz flicker corner. The prescaler PN is specified with two corner PN methods. The PNFloor measured at 500 MHz (which corresponding to frequency output at which the prescaler gives the additive PN), it is of −160 dBc/Hz, specified with 10 kHz corner frequency and 10 Hz 1/f corner frequency. 3.2 Simulation results 3.2.1 Resultant synthesiser system for E-band frequency ADLsimPLL software also allows the determination of the appropriate loop filter elements for the parameterisation of the desired synthesiser. Figs. 5 and 6 illustrate the simulated synthesiser circuits for E-band frequency with the specified values of third-order passive loop filter. To have more clarity, Table 1 summarises the component values of the resultant filter. Fig. 5Open in figure viewerPowerPoint Integer 70 GHz PLL frequency synthesiser Fig. 6Open in figure viewerPowerPoint Integer 80 GHz PLL frequency synthesiser Table 1. Filter component values ωp = 1 MHz, Δϕ = 45° (71–76 GHz) (81–86 GHz) C1 5.98 pF 5.27 pF R1 5.48 kΩ 6.22 kΩ C2 81.4 pF 71.6 pF R2 11.2 kΩ 12.7 kΩ C3 2.73 pF 2.40 pF 3.2.2 System analysis Although the PN can be guessed from the graph shown in Figs. 7 and 8, ADIsimPLL software can be configured to generate a specific PN at specific offset frequencies. Table 2 reports analysis from 1 Hz to 10 GHz for various results of PN effect on each component constituting the synthesiser in (71–76 GHz) and (81–86 GHz) range frequency. In the schematic representation, it can be seen that the crystal reference PN, prescaler noise and the chip noise decrease slowly and continuously. Fig. 7Open in figure viewerPowerPoint PN for each component in 70 GHz PLL synthesiser Fig. 8Open in figure viewerPowerPoint PN for each component in 80 GHz PLL synthesiser Table 2. PN of each component of PLL synthesizer for E-band frequency Freq., Hz Phase noise, dBc/Hz @ 70/80 GHz Total VCO Ref. Prescaler Chip Filter 1 −24.66/−23.55 −280.7/−280.7 −30.28/−29.16 −26.30/−25.18 −38.73/−37.62 −204.3/−203.8 10 −47.13/−46.02 −268.1/−268.1 −57.68/−56.57 −53.70/−52.59 −48.73/−47.62 −184.3/−183.8 100 −58.61/−57.50 −250.7/−250.7 −80.28/−79.16 −76.30/−75.18 −58.72/−57.60 −164.3/−163.8 1.00k −68.55/−67.44 −231.1/−231.1 −100.6/−99.49 −96.66/−95.55 −68.56/−67.45 −144.3/−143.8 10.0k −77.27/−76.16 −211.1/−211.1 −117.7/−116.6 −116.1/−115.1 −77.27/−76.16 −124.3/−123.8 100k −81.50/−80.39 −188.2/−188.2 −120.4/−119.3 −124.8/−124.2 −81.52/−80.41 −104.4/−103.9 1.00M −79.94/−78.87 −157.7/−157.7 −118.3/−117.2 −123/−122.4 −80.27/−79.15 −91.35/−90.79 10.0M −115.7/−114.7 −159.9/−159.9 −154.8/−153.7 −159/−158.9 −116.9/−115.7 −121.9/−121.3 100M −157/−156.7 −160/−160 −211.7/−210.6 −216.3/−215.8 −173.7/−172.6 −160.1/−159.6 1.0G −160/−160 −160/−160 −271.6/−270.5 −276.3/−275.7 −233.7/−232.6 −200.1/−199.6 10.0G −160/−160 −160/−160 −300/−300 −300/−300 −292.8/−291.8 −240.1/−239.6 Within the loop bandwith, the total noise is dominated by ADF4155-PLL chip (which contains PFD/CP and divider elements). It is amplified then attenuated at offsets much greater than the specified loop bandwidth (1 MHz). Outside the loop bandwidth, VCO oscillator noise is often the dominant noise source. Even if it is amplified inside the loop bandwidth, it remains constant after reaching it. Regarding the loop filter noise, it is mainly due to the resistance noise but tends to decrease when it reaches 1 MHz loop bandwidth. Figs. 9 and 10 show the gain amplitude and the phase of the open-loop transfer function required to analyse the stability of the PLL. By projecting 0 dB on the specified loop frequency (1 MHz), the phase is at its maximum and equals 135° which means and confirms that the designed synthesiser is at 45° phase margin far from the instability. Regarding the transfer function of the closed-loop response, Figs. 11 and 12 show that around the loop bandwidth, the gain transfer function has a large amplitude. It is constant until it reaches 1 MHz loop bandwidth and then decreases rapidly. This means that this function represents the gain of the noise in the pass-band loop caused by the division ratio which is attenuated beyond the loop frequency. Association of the open- and closed-loop responses lead to the error loop response. By examining Figs. 13 and 14, it can be seen that the gain amplitude looks like a high pass filter and reaches 2.29 dB at 1 MHz loop bandwidth. Fig. 9Open in figure viewerPowerPoint Open-loop response for 70 GHz PLL synthesiser Fig. 10Open in figure viewerPowerPoint Open-loop response for 80 GHz PLL synthesiser Fig. 11Open in figure viewerPowerPoint Closed-loop response for 70 GHz PLL synthesiser Fig. 12Open in figure viewerPowerPoint Closed-loop response for 80 GHz PLL synthesiser Fig. 13Open in figure viewerPowerPoint Frequency modulation response for 70 GHz PLL synthesiser Fig. 14Open in figure viewerPowerPoint Frequency modulation response for 80 GHz PLL synthesiser Figs. 15 and 16 show the simulation results of the reference spurs generated by 1 nA leakage CP current at the multiple of 50 MHz reference frequency. To have more clarity, the three first reference spur values are reported in Table 3. Fig. 15Open in figure viewerPowerPoint Reference spurs for 70 GHz PLL synthesiser Fig. 16Open in figure viewerPowerPoint Reference spurs for 80 GHz PLL synthesiser Table 3. Three first reference spurs for E-band frequency Reference spurs @ offset frequency, MHz (71–76 GHz), dBc (81–86 GHz), dBc 50 −113 −112 100 −131 −130 150 −142 −141 To close this analysis, Table 4 presents the RMS jitter calculated from 1 Hz to 10 GHz for both 70 and 80 GHz E-band frequency. Table 4. RMS Jitter for E-band frequency E-Band frequency RMS Jitter, fs (71–76 GHz) 399 (81–86 GHz) 401 3.2.3 Validation results and comparison of state-of-the-art mmW frequency synthesisers The previous section allowed presenting an analysis of simulation results, corresponding to the design of PLL frequency synthesiser able to generate the whole E-band frequency. In the frequency domain, PLL system performances are characterised in terms of PN, reference spurs and RMS jitter. In this work, a simulation with 45° phase margin, 1 MHz loop bandwidth and 1 nA leakage current leads to design a synthesiser with low noise, low jitter and low gain amplitude of reference spurs. Indeed, in PN analysis, this one is done following the evolution of the overall PN of the system, before after and when it reaches the loop bandwidth. From Table 2, it can be seen that the total noise is low in gain. It is approximately around −80 and −114 dBc/Hz at 100 kHz and 10 MHz, respectively. Regarding the reference spurs generated by the CP component, it can be conducted that the three first ones present a very low gain which will lead to the fast locking of the loop. Moreover, in addition to the low RMS jitter shown in Table 4, the resultant filter of the proposed synthesiser is characterised by resistance and capacitor 20 GHz mmW-Band Frequency, GHz Phase noise@100 kHz, dBc/Hz Phase noise@1 MHz, dBc/Hz Phase noise @10 MHz, dBc/Hz Jitter, fs Spurs Architecture References — 23.8–30.2 −70 NA −111 780 NA fractional-N [6] — 26.2–32.4 NA −101.4 NA 456 NA integer-N [9] −100.2 629 fractional-N K-band 27.5–29.6 −78 NA −126 510 −80 fractional-N [11] K-band 27.72–33.65 NA −104 NA NA <−50 integer-N [27] — 39.1–41.6 −58 NA −115 2100 −54 fractional-N [28] — 46.4–58.1 NA NA −118 NA NA integer-N [29] — 53.8–63.3 NA −88.3 NA NA <−40 integer-N [30] — 56–62 −63 NA −109 NA −75 fractional-N [31] — 56.4–63.4 NA −96.6 NA 522.9 NA — [32] V-band 58.1–65 NA NA −117 — <−52 integer-N [33] E-band 71–76 −81.5 −79.94 −115.7 401 −113 integer-N (this work) 81–86 −80.39 −78.87 −114.7 399 −112 4 Conclusion In this paper, we have presented a model of an integer PLL frequency synthesiser for E-band frequency for the next 5G communication systems. PN characteristic can degrade the quality of output waveform. So, in this work, based on the theoretical analysis of the PN for the PLL system, an accurate prediction of this criterion in each component constituting the circuit is processed. Also, other important PLL characteristics as RMS jitter and spurs are presented to assess the performance of the global system. Analysis of the circuit on ADIsimPLL. Vers. 4.30.03, allowed to compare it with other synthesisers designed for mmW frequencies. Through this analysis, we can conclude that the proposed synthesiser using ADF4155-PLL chip from analogue devices, has presented powerful and significant results that can meet the 5G system requirements. However, the technique used for its design could possibly be applied to the new 'ADF41513-chip'. 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Solid-State Circuits, 2013, 48, (7), pp. 1710– 1720 Citing Literature Volume9, Issue1January 2020Pages 23-28 FiguresReferencesRelatedInformation
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