Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process
2019; Institute of Electrical and Electronics Engineers; Volume: 40; Issue: 11 Linguagem: Inglês
10.1109/led.2019.2940696
ISSN1558-0563
AutoresShen‐Yang Lee, Hanwei Chen, Chiuan-Huei Shen, Po‐Yi Kuo, Chun-Chih Chung, Yu-En Huang, Hsin-Yu Chen, Tien‐Sheng Chao,
Tópico(s)MXene and MAX Phase Materials
ResumoFor the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of 5.3 × 9 nm 2 and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit a remarkable I on -I off ratio of more than 108. We demonstrated stacked channels, double layers, GAA NC-FET with a threshold voltage (V TH ) of 0.61 V, and a superior subthreshold behavior with an average and minimum sub-V TH slope of 43.85 and 26.84 mV/dec, respectively. An additional ZrO 2 seed layer was inserted under the Hf 1-x Zr x O 2 layer to improve ferroelectric crystallinity. Thus, the conventional crystallization annealing step can be omitted due to the presence of the orthorhombic phase (o-phase) before further post-metal annealing (PMA).
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