High step‐down/high step‐up interleaved bidirectional DC–DC converter with low voltage stress on switches
2019; Institution of Engineering and Technology; Volume: 13; Issue: 1 Linguagem: Inglês
10.1049/iet-pel.2018.6164
ISSN1755-4543
AutoresSara Mousavinezhad Fardahar, Mehran Sabahi,
Tópico(s)Silicon Carbide Semiconductor Technologies
ResumoIET Power ElectronicsVolume 13, Issue 1 p. 104-115 Research ArticleFree Access High step-down/high step-up interleaved bidirectional DC–DC converter with low voltage stress on switches Sara Mousavinezhad Fardahar, Sara Mousavinezhad Fardahar Faculty of Electrical and Computer Engineering, University of Tabriz, 29th Bahman Blvd, Tabriz, IranSearch for more papers by this authorMehran Sabahi, Corresponding Author Mehran Sabahi sabahi@tabrizu.ac.ir Faculty of Electrical and Computer Engineering, University of Tabriz, 29th Bahman Blvd, Tabriz, IranSearch for more papers by this author Sara Mousavinezhad Fardahar, Sara Mousavinezhad Fardahar Faculty of Electrical and Computer Engineering, University of Tabriz, 29th Bahman Blvd, Tabriz, IranSearch for more papers by this authorMehran Sabahi, Corresponding Author Mehran Sabahi sabahi@tabrizu.ac.ir Faculty of Electrical and Computer Engineering, University of Tabriz, 29th Bahman Blvd, Tabriz, IranSearch for more papers by this author First published: 01 January 2020 https://doi.org/10.1049/iet-pel.2018.6164Citations: 3AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract A DC–DC bidirectional converter which has low voltage stress on its semiconductor elements is presented in this study. This study presents a novel interleaved coupled-inductor-based non-isolated bidirectional DC–DC converter which is able to provide a high voltage gain conversion ratio. The high voltage gain of the proposed converter is achieved through its symmetrical topology with coupled inductors in its structure. Based on the fact that the voltage of the high-voltage side is shared between the two separate modules of the converter, the voltage stress across the switches is decreased. There are two blocking capacitors in the primary side, which help the converter to have symmetrical topology. Also, the switching pattern of the proposed converter is simple and the converter is able to provide a single voltage gain for the whole range of duty cycle. The theoretical results are approved through the prototype of the converter for 400 W. 1 Introduction DC–DC bidirectional converters can be utilised in versatile applications such as uninterrupted power supplies, renewable power generation, electric vehicles and micro-grids [1, 2]. In the mentioned applications, batteries and a conversion unit, which must be a bidirectional converter is needed. The required voltage range varies according to the application defined for the converter. As mentioned, the batteries have a crucial role in the renewable energy applications. Based on the volume of the batteries that are connected with each other, the voltage range of the conversion unit, including the converter will be determined [3]. The voltage produced through the renewable energies are low, then, for the applications that need higher voltages a step-up converter would be required and for applications that need high currents a step-down converter would be needed, as a result, a bidirectional DC converter would be preferred [4]. High voltage gain bidirectional converters are divided into two types of non-isolated and isolated converters, in other words, converters with transformers and converters which are non-isolated. Any of these converters have their own advantages and constraints. In spite of the fact that bidirectional DC–DC converters have to provide high voltage gains, they should also be satisfying from other aspects such as high transferring power and low voltage stress on semiconductor elements to achieve high efficiency [5, 6]. Interleaving can decrease the voltage stress on the semiconductor elements of the bidirectional DC converters. Therefore, by interleaving the structure, the voltage stress on semiconductor elements will be significantly decreased. Conventional buck–boost converters are the simplest type of non-isolated DC converters that can be used in both buck and boost modes. However, the conventional buck–boost converters suffer from high voltage stress on the power switches and low conversion ratios. In [7, 8], conventional buck–boost DC converter has become soft switched with the coupled-inductor-based auxiliary circuits and its stress on switches is decreased. High voltage gain buck–boost converters are presented in [9-11]. Also, coupled-inductor-based converters are presented in [12-21]. However, these coupled-inductor-based converters suffer from high current stress at their low voltage terminal side [12-19]. Moreover, hard switching and high voltage spikes on switches which are caused by the leakage inductances of the implemented coupled inductors in [13] have decreased the performance of this converter. By utilising the Sepic-derived topology inside the buck–boost converter and using two coupled-inductors in [20, 21], soft-switched high voltage gain bidirectional DC–DC converters with low input current ripples at the low voltage side are achieved. However, these converters have only a single phase at their low voltage sides that has limited their power conversion ratios. For high power applications, to decrease the current stress at the low voltage side of the converter, previously presented bidirectional DC converters can be parallel-connected or interleaved with interleaved switching patterns. However, with this method, the number of components would be large and the cost will be high. In [22], two converters with soft switching capability are introduced. In these converters, four switches are connected interleaved, but on the other hand, the power circuit components are doubled and eight switches are implemented. Interleaved structures that are designed to be interleaved and are not created by interleaving two separate circuits are presented in [23-25]. The converter presented in [23] has low voltage conversion ratio and the voltage stress on its active switches is considerable. In [24], a coupled-inductor-based DC–DC interleaved bidirectional converter with four-phases is proposed. In this converter, each phase consists of an inductor, two switches and one capacitor. However, the high voltage gain is achieved with numerous elements and high cost. The converter presented in [25] is a high voltage gain DC bidirectional converter combining with the conventional interleaved bidirectional converters with a voltage multiplier cell. In this converter the inductors are at the low voltage side, therefore, the effective current is high and this converter suffers from high conduction losses. Also, there are switched-capacitor-based converters as in [26] which have utilised switched-capacitor cells to achieve high conversion ratios. However, these converters suffer from high number of circuit components. This study proposes a new interleaved bidirectional DC–DC converter, which has high conversion ratios in both buck and boost operations. The proposed converter has interleaved topology with a coupled inductor in its structure which is able to provide high voltage and current conversion ratios. By interleaving and parallel-connection of the modules of the converter, the voltage stress across the active switches is decreased and the voltage gain is increased. The coupled inductor is implemented to increase the voltage gain. 2 Proposed high step-down/high step-up converter The proposed bidirectional converter is shown in Fig. 1a. Two coupled inductors are used to achieve the high voltage conversion ratio. Each coupled inductor has the magnetising inductors and , and leakage inductors and . The primary and secondary windings of each coupled inductor have and turns, respectively. Therefore, the turns ratio of the coupled inductors are considered as , and . The capacitance and are considered large enough. The diodes of , , and are the internal diodes of the switches , , and , respectively. Fig. 1Open in figure viewerPowerPoint Proposed high step-down/ high step-up converter and its equivalent circuits in buck and boost operations (a) Proposed high step-down/ high step-up converter, (b) Equivalent circuit in buck operation, (c) Equivalent circuit in boost operation The power circuits of the proposed converter in buck and boost operations are shown in Figs. 1b and c, respectively. Considering Figs. 1b and c, it can be seen that for using the proposed converter in boost and buck operations, only the places of input voltage source and output load are changed. In the coupled inductors, the coupling coefficient K is defined as . In other words, the ratio of inductances and , is defined as . Since the capacitors and are considered large enough, the voltage across them can be considered as a constant voltage with magnitudes and , respectively. Therefore, the operation of the proposed converter is the same as the conventional interleaved converters and is the analysis for the two ranges of duty cycles larger and less than 0.5, based on that, the first and second phases of the proposed converter has symmetrical operations with 180° shift phases, which causes to have one conversion ratio for the whole range of duty cycles larger and less than 0.5. Meanwhile, the conventional interleaved boost converters based on the coupled inductors have two different voltage gains for two ranges of duty cycles larger and less than 0.5. As a result, in the proposed converter, the control of the output voltage by using one voltage gain can be easily implemented for the whole range of duty cycles. Where, the control of output voltage in the other conventional converters of the same type is complicated than the proposed converter. In the conventional converters, because the conversion ratio of the boost converter for duty cycles is higher than 0.5 is better, therefore, the conversion ratio has been presented for duty ratios higher than 0.5. The proposed converter is analysed under continuous conduction mode (CCM) condition for both boost and buck operations. Figs. 2 and 3 show the waveforms of the proposed converter for buck and boost operations, respectively. Equivalent circuits of buck and boost operations are illustrated in Figs. 4 and 5, respectively. Fig. 2Open in figure viewerPowerPoint Waveforms of the proposed converter for buck operation during one switching period (a) Waveforms for , (b) Waveforms for Fig. 3Open in figure viewerPowerPoint Waveforms of the proposed converter for boost operation during one switching period (a) Waveforms for , (b) Waveforms for Fig. 4Open in figure viewerPowerPoint Equivalent circuits of buck operation during one switching period for and (a) Mode 1 for and , (b) Modes 2 and 4 for , (c) Mode 3 for and , (d) Modes 2 and 4 for Fig. 5Open in figure viewerPowerPoint Equivalent circuits of boost operation during one switching period for and (a) Mode 1 for and , (b) Modes 2 and 4 for , (c) Mode 3 for and , (d) Modes 2 and 4 for 3 Operating principles of proposed converter for The voltage and current waveforms of the proposed converter is shown in Fig. 2a. Mode 1 [t0<t < t1]: In the first operating mode, the switches and are on, while, the other two switches and are off. The equivalent circuit of this mode is shown in Fig. 4a for the buck operation or Fig. 5a for the boost operation. By applying KVL and KCL in Fig. 4a or 5a, respectively, the following equations are obtained: (1) (2)By deriving from (2), and based on the voltage equations across the inductors and (3), the voltage is obtained by the following equation: (3)In the same way, by considering that is equal to , and equation , the voltage is obtained by the following equation: (4)Modes 2 and 4 [t1 ≤ t < t2 and t3 ≤ t < t4]: In the second and fourth operating modes, the switches and are on, while, the other two switches and are off. The equivalent circuit of these modes is shown in Fig. 4b for buck operation or Fig. 5b for boost operation. By applying KVL and KCL in Fig. 4b or 5b, same as mode 1, the voltages and are obtained as the following equation and (4), respectively. (5)Mode 3 [t2<t < t3]: In the third operating mode, the switches and are on, while, the two other switches and are off. The equivalent circuit of this mode is shown in Fig. 4c for buck operation or Fig. 5c for boost operation. By applying KVL and KCL in Fig. 4c or 5c, same as mode 1, the voltages and are obtained as (5) and the following equation, respectively: (6) 3.1 Voltage gain Based on the voltage balance law for the inductors and , the average voltage across the inductors would be equal to zero at the steady-state mode. Therefore, applying the voltage balance law for the inductors and , results in the following equations: (7) (8)Considering the same coupled inductors (, , ), (7) and (8) are simplified and the voltages on capacitors are obtained as follows: (9)According to Fig. 1a the following equation is always obtained: (10)Based on (9) and (10), the voltage conversion ratio between low and high voltage sources would be calculated as follows: (11)The voltage gains of the proposed converter in buck and boost operations are equal to and , respectively. 3.2 Voltage stress on switches and diodes According to Fig. 4a) or 5a, the voltage stress on switches , is calculated as follows: (12) (13) According to Fig. 4b or 5b, the voltage stress on switches and is calculated as (9) and (10), respectively. According to Fig. 4c or 5c, the voltage stress on switches and is calculated as (9). As a result, by neglecting the leakage inductances of coupled inductors (), the voltage stresses on the switches and during interval time of is calculated as follows: (14)By neglecting the leakage inductances of the coupled inductors (), the voltage stresses on the switches and during interval time of is calculated as follows: (15)Therefore, considering (11) and (12), the theoretical waveforms of the voltages on switches and diodes are plotted in Fig. 2. Note that in the mentioned interval time, the voltage stress on switches and diodes are as the calculated values in (11) and (12) and in the other intervals are equal to zero. 3.3 Average currents of inductors, switches and diodes Based on Fig. 1 and operation of the proposed converter during the four operating modes and the fact that the average currents of capacitors are equal to zero, the average currents of switches can be obtained as follows: (16) (17)where if the converter is considered ideal, the power balance law would be written as . Therefore, considering (11) the relation between low and high voltage side currents should be as . By considering that the average current switch of is equal to . Therefore, its transferred current to the primary winding of is equal to or . As a result, the current of is equal to . In the same way, the current of is calculated as . Consequently, average values of and can be obtained as follows: (18)According to Fig. 4 or 5, the current stress on switches and during the interval time of is calculated as follows: (19)According to Fig. 4 or 5, the current stress on switches and during the interval time of is calculated as follows: (20)By considering Fig. 4 or 5 and Fig. 2, the inductor currents ripple is calculated as follows: (21)The maximum and minimum () values of the currents and are obtained as follows: (22) (23)Based on Figs. 1a and b, in the buck operation of the proposed converter the output current is calculated as . Therefore, in the above equations can be written, depend on the output current as for the buck operation. Based on Figs. 1a and c, in the boost operation proposed of converter the output current is calculated as . Therefore, considering , in the above equations can be written, depend on the output current as for the boost operation. Based on Fig. 4 or 5, the current of during mode 1 and during mode 3 are . The current of during modes 2, 3 and 4 and during modes 1, 2 and 4 are . Therefore, the current through the capacitors and during interval times are calculated as the following equation: (24) 3.4 Design considerations Since the operation of the proposed converter is analysed under CCM, the acceptable values of inductances of inductors for CCM operation is calculated in this part. For this aim, the average value of the currents passing through the inductances has to be higher than half of their current ripple [IL>(ΔIL/2)]. As a result, based on (18) and (21), the following inequalities have to be verified to the proposed converter operate under CCM operation. (25)As mentioned before the relation between leakage and magnetising inductances depend on the coupling coefficient is . Moreover, in the buck and boost operations is obtained as and , respectively. As a result, in the buck operation, the magnetising inductances would verify the following inequality: (26)In the same way, in the boost operation, the magnetising inductances would verify the following inequality: (27)Considering (19) and (20), since the average current flowing through the capacitors , and , during the interval time of is equal to , therefore, the minimum value of these capacitors for their maximum voltage ripple of would obey the following inequality: (28)As a result, in the buck operation, the capacitors and would verify the following inequality: (29)In the same way, in the boost operation, the capacitors and would verify the following inequality: (30) 4 Operating principles of proposed converter for The voltage and current waveforms of the proposed converter is shown in Fig. 2b. Mode 1 [t0<t < t1]: In the first operating mode, the switches and are on, while, the two other switches and are off. The equivalent circuit of this mode is same as that for which is shown in Fig. 4a for the buck operation or Fig. 5a for the boost operation. As a result, (1)–(4) are verified for this mode. Modes 2 and 4 [t1 ≤ t < t2 and t3 ≤ t < t4]: In the second and fourth operating modes, the switches and are on, while, the two other switches and are off. The equivalent circuit of these modes is shown in Fig. 4d for the buck operation or Fig. 5d for the boost operation. By applying KVL and KCL in Fig. 4b or 5b, same as mode 1, the voltages and are obtained as equations and (3) and (6), respectively. Mode 3 [t2<t < t3]: In the third operating mode, the switches and are on, while, the two other switches and are off. The equivalent circuit of this mode is same as that for which is shown in Fig. 4c for buck operation or Fig. 5c for boost operation. As a result, the voltages and are obtained as (5) and (6), respectively. Consequently, based on the equations of voltages and during different modes and Fig. 2b, (7)–(11) are also obtained for . Moreover, the voltage stresses on the switches and during interval time of is calculated as (14) and the voltage stresses on the switches and during interval time of is calculated as (15). Furthermore, (16)–(29) are also verified for this operation. 5 Performance comparison In this section, a comparison among the proposed bidirectional converter and four other recent converters is presented. All the selected converters for comparison have similar characteristics as the proposed one. There are different criteria selected for comparison, which are shown and listed in Table 1. The comparison criteria are including the operating duty cycle to show the fact that not all of the converters can be operated in the whole range of duty cycles, the number of phases which is very significant for the easy control of the converter, number of voltage gain equation which plays a significant role in practical implementation and application of the converter, the conversion ratios of the converters (G), normalised voltage stress on switches (), normalised total voltage stress on switches (), the number of switches (NS), number of inductors (NI), number of coupled inductors , number of capacitors (NC) and also the total number of components (Ncomponent). As far as the proposed converter has a single constant conversion ratio for the whole range of the duty cycles, the proposed converter has better performance in practical applications. Table 1. Comparing results of bidirectional non-isolated high voltage gain converters DC–DC Converters Operating duty cycle Number of phases Number of voltage gain equation for 0 < D 0.5 2 2 [16] D > 0.5 2 2 4 [24] D > 0.5 2 2 3 [26] 0 < D<1 1 1 9 proposed converter 0 < D<1 2 1 Efficiency NS NI NCI NC NComp — %92.6 For 200W 6 2 1 3 12 — %92.5 For 200W 4 4 1 3 12 96 For 400W 8 — 2 5 15 %94.5 For 100W 12 — — 8 20 %95.2 For 400W 4 — 2 2 8 In the bidirectional DC–DC converters, the conversion ratio can be an acceptable parameter of comparison. As shown in Fig. 6a, the voltage gain comparison of the converters versus the applied duty cycles is presented. Through this comparison, the converter has a constant conversion ratio for all duty cycles, then the behaviour of the converter is easy to predict. Moreover, in Fig. 6, the turn ratios of the compared converters with coupled inductors are considered as n = 1. Fig. 6Open in figure viewerPowerPoint Comparison of the proposed converters with other recently presented converters from two aspects of (a) G versus D, (b) Also, in bidirectional converters, due to the fact that the converter will be operated in both buck and boost operations, then, the converter will experience the high voltage and high current density. As a result, the voltage stress on the semiconductor elements has to be low to make the converter suitable for practical applications. As shown in Fig. 6b, the total voltage stress on its switches is rather low and in comparison, it has lower stress on semiconductor elements, even though the other compared converters have interleaved structures which have reduced their voltage stresses on active switches. Besides, the proposed converter does not have the drawback and constraint that interleaved converters have. From Table 1, one can easily understand that the proposed converter has obtained such a high conversion ratio with a much smaller number of components and without increasing the size of the elements, due to the fact that the inductance of the coupled inductors is low and the current passing through them is not considerable. Also, another feature that the proposed converter has is the number of passive elements which is less than other compared converters. 6 Experimental results To reconfirm the analytical results of boost and buck operations of the proposed converter, the experimental results in Figs. 7 and 8 are extracted. The values of different elements are summarised in Table 2. Table 2. Experimental parameters Parameters Values input voltage buck operation boost operation duty cycle switching frequency inductors , capacitors output resister buck operation boost operation switches IRFP4668PbF Fig. 7Open in figure viewerPowerPoint Experimental results of buck operation (a) Output voltage, (b) Voltage stresses on switches, (c) Inductors currents, (d) Current stresses on switches Fig. 8Open in figure viewerPowerPoint Experimental results of boost operation (a) Output voltage, (b) Inductors currents, (c) Current stresses on switches 6.1 Buck operation The values of input voltage and output resistance for the proposed converter in the buck operation are considered as and , respectively. According to (9), the capacitors’ voltages for the parameters are calculated as . Therefore, from (10) or (11), the output voltage is calculated as which is verified by experimental result in Fig. 7a. As a result, the output power is calculated as . Considering , , D = 0.4 fs = 30 kHz and based on (26), the magnetising inductances to achieve CCM operation of the proposed converter are calculated as . Moreover, considering (29), the capacitors values to have minimum voltage ripple across them (ΔVc = 0.01Vc) are calculated as . So, the inductances and capacitors values are selected as shown in Table 2. According to (14) and Fig. 2a, the voltage stress on the switch () during modes 2, 3 and 4 (during interval time of ) and switch () during modes 1, 2 and 4 (during interval time of ) are calculated as . According to (15) and Fig. 2a, the voltage stress on switch () during mode 1 (during interval time of DTs) and switch () during mode 3 (during interval time of DTs) are calculated as . Fig. 7b shows the experimental results of the voltages across the switches, which are very close to the calculated theoretical values. Moreover, the theoretical voltage waveforms in Fig. 2a reconfirm Fig. 7b. Based on (18), the average value of inductors’ currents of , are calculated as . Moreover, according to (22) and (23), the maximum and minimum values of the inductors’ currents are calculated as and , respectively. Fig. 7c shows the experimental results of the inductors’ currents, which have the same maximum and minimum values as calculated by the analytical results. The experimental results of the currents of switches are illustrated in Fig. 7d. Considering the waveforms of and in Fig. 2a and, the maximum current stress of switches and for the buck operation is calculated as . Top figure of Fig. 7d shows the current of switches and has almost the maximum current stress as calculated theoretical value. Considering the waveforms of and in Fig. 2a, the maximum current stress of switches and for buck operation is calculated as which can be verified by the bottom figure of Fig. 7d. 6.2 Boost operation The values of input voltage and output resistance for the proposed converter in boost operation are considered as and , respectively. Same as buck operation, from (11), the output voltage is calculated as which is verified by experimental result in Fig. 8a. As a result, the output power is calculated as . Therefore, the experimental results of the buck and boost operations extracted the same output power, which causes that the maximum and minimum values of inductors currents and switches currents in boost operation form the aspect of magnitude were equal to them in buck operation with opposite direction. In other words, comparing the waveforms Figs. 7c and d with respect the waveforms Figs. 8b and c, results currents waveforms in boost and buck operations for the same output power are same as each other and just the direction is changed. The voltages on switches in boost operation are the same as buck operation in Fig. 7b. In Fig. 9, transient experimental results for both the buck and boost operations are extracted for input voltage variations, load step changes and the output current variations. Fig. 9Open in figure viewerPowerPoint Experimental transient results for buck and boost operations for (a) Input voltage variations, (b) Load step changes, (c) Output current variations Fig. 10 illustrates the implemented prototype of the proposed converter. Fig. 11a shows the comparison result of the efficiency in the proposed converter and the presented conventional converters in Table 1 versus output power. In [15], the efficiency is plotted under the frequency switching of and duty cycle of . In [24], the efficiency is plotted under the frequency switching of and duty cycle of . In [26], the efficiency is plotted under the frequency switching of . Fig. 11b shows the efficiency of the proposed converter versus duty cycle for the output power of . Fig. 10Open in figure viewerPowerPoint Implemented prototype of proposed converter Fig. 11Open in figure viewerPowerPoint Measured efficiency versus output power and duty cycle (a) Comparing measured efficiency versus output power, (b) Measured efficiency versus duty cycle The conduction and switching losses of the proposed converter and then the theoretical efficiency is calculated in this section. The internal resistors of the diodes , switches , inductors , capacitors , forward drop voltage of diodes and forward drop voltage of switches are considered for calculating the power losses. The average values of currents of switches and diodes are concluded from (16) and (17). According to (16) and (17), conduction losses of the switches (, ) and diodes ( and ), the switching losses for the switches (, ) and diodes (, ), total power loss of switches , total conduction loss of inductors , total core loss of inductors (), total conduction loss of capacitors and total power loss are calculated as shown in Table 3. Table 3. Power loss calculation for all components of proposed converter , , , , , , , , so, in (kW/m3) from datasheet , so, in (kW/m3) from datasheet , , In Fig. 11b, the extracted efficiency of the proposed converter for the input voltage of and output power of versus duty cycle is shown. For low voltage of , the switches and are considered as IRFP4668PbF (200 V, 130 A). Therefore, the parameters of switches are as , , , and . The used diodes and are considered as DPG60I300HA (300 V, 60 A). Therefore, the diodes’ parameters are , , and . The internal resistors of capacitors and inductors are considered as and , respectively. In Table 3, the power loss calculation for all the components of the proposed converter is presented. In Table 3, the parameters of the implemented circuit are as , , and and the peak to peak flux density and are calculated as and .respectively, Considering the datasheet of utilised inductor core of PC40EE30-Z, there is a curve that indicates the power loss density in kW/m3 as a function of peak flux density of and switching frequency (f). As a result, the core loss density of the first inductor with is equal to . Similarly, the core loss density of the other inductor with is obtained as . As a result, from the datasheet, the effective volume of core PC40-EE30-Z is equal to . 7 Conclusion In this paper, a DC–DC bidirectional converter with low voltage stress on its switches and diodes is presented. The proposed converter is a new bidirectional interleaved coupled-inductor-based non-isolated DC–DC converter. It is able to provide a high voltage gain conversion ratio in the boost mode and high current conversion ratio in the buck mode. The high voltage gain of the proposed converter is achieved through its symmetrical topology and the utilised coupled inductors in the structure. Owing to the fact that the converter has parallel-connection of two modules, voltage of the high-voltage side is shared, consequently, the voltage stress across the switches are decreased. Meanwhile, the topology is symmetrical which makes the design and implementation easier. The switching pattern of the proposed converter is simple and the converter has a single voltage gain for the whole range of duty cycles. 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