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Isolated boost converter based high step‐up topologies for PV microinverter applications
2020; Institution of Engineering and Technology; Volume: 13; Issue: 7 Linguagem: Inglês
10.1049/iet-pel.2019.1190
ISSN1755-4543
AutoresAntónio Manuel Santos Spencer Andrade, Mário Lúcio da Silva Martins,
Tópico(s)Multilevel Inverters and Converters
ResumoIET Power ElectronicsVolume 13, Issue 7 p. 1353-1363 Research ArticleFree Access Isolated boost converter based high step-up topologies for PV microinverter applications António Manuel Santos Spencer Andrade, Corresponding Author antoniom.spencer@gmail.com orcid.org/0000-0001-6098-0475 Federal University of Santa Maria, BrazilSearch for more papers by this authorMário Lúcio da Silva Martins, Federal University of Santa Maria, BrazilSearch for more papers by this author António Manuel Santos Spencer Andrade, Corresponding Author antoniom.spencer@gmail.com orcid.org/0000-0001-6098-0475 Federal University of Santa Maria, BrazilSearch for more papers by this authorMário Lúcio da Silva Martins, Federal University of Santa Maria, BrazilSearch for more papers by this author First published: 01 May 2020 https://doi.org/10.1049/iet-pel.2019.1190Citations: 1AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinked InRedditWechat Abstract In this study, a family of isolated boost DC–DC converters is proposed and evaluated. This family is built by the combination of an isolated current fed converter with high-voltage gain techniques. The evaluated cells are switched inductor, switched capacitors, reduced redundant power processing and a mixed of switched inductor and switched. So, the proposed family has four different isolated high step-up DC–DC converters. To evaluate this family, a comparative study of the significant features was performed. This study comprises features such as principle of operation, derivation of static voltage gain, current and voltage stress on the components, component stress factor, number of components, power losses, power density and cost. By these evaluations, the key features, limitations and restrictions of each converter were acknowledged. In this way, one can gather all the theoretical knowledge of each of the analysed converters and estimate which one will have better performance in the laboratory. To validate the theoretical analysis, four prototypes were built according to PV AC-module specifications 200 W. 1 Introduction Solar energy has become very popular as a distributed energy conversion system. This system has grown in the last few years. The interest in solar energy is due to the increasing efficiency of solar cells as well as developments of the manufacturing technology for photovoltaic (PV) panels, and it is re-enforced by the environmental impact caused by non-renewable sources [1-5]. For small rooftop or building-integrated PV systems, associating power generation and energy storage into the Smart Grid concept has become an interesting solution. Nevertheless, for such small residential rooftop systems, the grounding of a PV system usually deserves special consideration not only for safety reasons [6] but also to lessen the effects of unpredictable lighting and other surges. Indeed, some countries provide mandatory Standard and Regulations that grid-connected PV systems must comply with; for instance standards such as IEEE 1547 [7], IEC 61727, and NEC 690 [8]. Thus, in many cases, as long as the neutral conductor of the single-phase utility is also grounded, a double grounding inverter topology is compulsory. In addition, galvanic isolation eliminates the grid leakage current problems [9]. Residential rooftop systems are commonly located in large cities and urban environments, but prominent partial shading effect and other PV panel mismatch conditions may cause a relevant reduction in electric power production. Augmenting the power flow fluctuation and postponing the investment payback time [10]. To reduce the probability of mismatching occurrences, distributed electronic circuits with decentralised maximum power point tracking PV systems have been often employed [11]. One possible solution is the PV module integrated converter (MIC). It is composed of a DC/DC converter and a DC/AC converter. This system is attractive because it tracks the maximum power point of each PV module individually, providing modularity and flexibility in implementation and maintenance [12]. According to [13], there are two types of MICs, i.e. those with a transformer and without a transformer. The transformer in use can be a high-frequency (HF) transformer on the DC/DC side or a low-frequency (LF) transformer on the DC–AC side. In addition to stepping up the voltage, it plays an important role in safety by providing galvanic isolation, thus eliminating leakage current, avoiding dc current injection into the grid and creating the risk of electric shock of the service personnel [13-15]. As PV modules offer very low voltage in comparison to DC bus or AC grids, a high conversion ratio is the primer concern of DC/DC conversion. Moreover, other characteristics that must be achieved for these types of converters are high efficiency, power density, lower cost, low voltage and current in the components [16]. In the last few years, different isolated topologies have been proposed. Therefore, the need to look for new solutions is evident [17-20]. In addition, since these converters require two or more drive signals, control and drive circuit complexity will increase. A simple solution of a DC/DC converter is a step-up isolated boost converter (IBC) (Fig. 1). It is attractive in applications such as PV MIC, for reasons that include galvanic isolation, simplicity of operation, and the fact that the high input current of the PV source is split between two inductors. Theoretically, the high-voltage gain can be achieved by raising its duty cycle (D) or the turns-ratio (N) of the transformer. It should be emphasised that the IBC operates only with a duty cycle D>0.5, to ensure demagnetisation of the transformer. However, an IBC presents high power losses when increased D; therefore, the efficiency of the converter decreases and the voltage across the converter components increases. In addition, if the N of the transformer increases, leakage of inductance energy in the transformer causes high voltage spikes in the switches and diodes, reducing system efficiency. Therefore, in order to reduce voltage spikes, dissipative clampers, an addition to a soft switching circuit, can be used. So, to achieve good performance, the circuit techniques feature must be for voltage gain and also to clamp the spikes [13, 14, 16]. This increases converter complexity. Thus, one needs to search for solutions that increase the gain of the converter and eliminate the problems mentioned above. Fig. 1Open in figure viewerPowerPoint Isolated boost topology (IBC) In recent years, many voltage step-up techniques have been studied, such as switched inductor (SI), switched capacitors (SCs), a mixed of SI and super-lift (SISL) charge pumping, reduced redundant power processing (R2P2) and so on [21-28]. For this reason, in the literature, different proposals of a high-voltage gain DC/DC converter have been presented with the aim of achieving high efficiency. To achieve such a goal, in this paper, different circuit techniques are associated with arranging the IBC; this way, four high-voltage gain isolating converters are presented. These techniques can be associated with the primary or secondary side of the transformer of the IBC. Thus, different characteristics can be addressed for an evaluation of the best technique that can be associated with the converter. For this purpose, a concise and detailed comparison of these topologies was carried out. Also, for voltage gain derivation, the following parameters were evaluated: principle of operation; voltage and current stress; stress factor; number of components; estimated power losses; power density; and relative cost. To achieve such a goal, first, a brief explanation of the converters is given in Section 2. In Section 3, a comparative evaluation of the converters is reported. In Section 4, the experimental results are discussed. Finally, in the conclusion section, the advantages and disadvantages of each evaluated topology are highlighted. 2 Evaluation of different step-up techniques applied to an isolated boost DC–DC converter Based on the discussion of the previous section, the points x, y and w, z are shown in grey in the IBC (Fig. 1). In the set of points yw, on the left side, the Input Port of IBC is defined. In the Input Port, different voltage step-up techniques can be associated, such as SI, SC, a mixed of SISL charge pumping, R2P2, QZ source (QZs) [29], different charge pump [30]. On the other hand, in the points wz, on the right side, the Output Port of IBC is defined. In the Output Port, it can be associated with different voltage multiplier rectifiers [31]. Thus, in the following sections, some techniques are presented and evaluated and, afterwards, different high-voltage gain topologies based on the IBC are generated and proposed. 2.1 Evaluation of voltage gain techniques In the Input Port, some voltage gain techniques can be used by replacing the inductors (L1 and L2) of IBC. Fig. 2 shows four main voltage gain techniques. To provide further information about these techniques, a detailed analysis of the switched inductor technique (Fig. 2a) is given below. It should be noted that applying the same principle has all the information needed for the other techniques. Fig. 2Open in figure viewerPowerPoint Voltage gain techniques (a) SI cell, (b) SI cell and SL charge pump (SISL) cell, (c) R2P2 cell, (d) QZs cell For the SI cell, this technique is based on the magnetisation of the two inductors (L1 and L2) in parallel with a DC voltage (usually the input voltage of the converter) and, consequently, the output voltage of the converter increases when these inductors are in a series (when demagnetising happens). In the magnetisation stage of the inductors, it is implied that the voltage difference Vxy is greater than zero, Vxy>0; and in the demagnetising stage of the inductors, Vxy 0.5. Therefore, QZs cells cannot be associated with IBC. Thus, only SI, SISL and R2P2 cells will be associated with the IBC. Table 1. Voltage gain of each cell Cells Voltage gain SI SISL R2P2 QZs Fig. 3Open in figure viewerPowerPoint Stage operation of the SI cell (a) Vxy>0, magnetisation of inductors, (b) Vxy<0, demagnetisation of inductors Fig. 4Open in figure viewerPowerPoint Key waveforms of the SI cell Fig. 5Open in figure viewerPowerPoint Voltage gain of each cell versus duty cycle The Output Port can be associated with different voltage multiplier rectifiers. These techniques are usually associated with the output of DC–DC converters that have a transformer. Basically, it can be said that there are two types of rectifiers: half-wave (Figs. 6a and b); full-wave (Figs. 6c and d). Fig. 6a shows the topology of a half-wave voltage multiplier rectifier. For Vwz 0, capacitor Co2 (Vo) charges from the sum of the voltages Vwz and VCo1, Vo = Vwz + VCo1 = 2Vwz. Fig. 6b shows a half-wave voltage triplicator rectifier. In this structure, the input voltage (Vwz) from the capacitors (Co1 and Co2) is doubled, and the input voltage is connected sequentially with these components, when Vwz 0, the output voltage Vo is equal to the Vwz in a series with the capacitors (VCo1 and VCo2), so the Vo = 3Vwz. For these rectifiers, for Vwz>0 and Vwz<0, the circulating current (iwz) for each case is different. This causes the transformer to have DC current levels, which leads to saturation. Consequently, it makes it impossible to associate these techniques in the IBC. For the full-wave rectifier, Fig. 6c shows the voltage doubler rectifier. As can be seen, this structure is intrinsic to the IBC. For Vwz 0, capacitor Co2 (VCo1) charges from the sum of the voltages Vwz. The capacitors Co1 and Co2 are stacked, where the output voltage is Vo = VCo1 + VCo2 = 2Vwz. Finally, another well-known full-wave rectifier is the Cockcroft Walton (CW) voltage multiplier, as shown in Fig. 6d. In the generalised circuit structure of the technique, the voltage multiplier Cockcroft–Walton, the odd capacitors (Co1, Co3, etc.) and even capacitors pairs (Co2, Co4, etc.) are charged by Vwz 0, respectively. The output voltage is m times greater than the input voltage (Vwz), i.e. Vo = mVwz, where m is equal to the number of capacitors. Thus, this technique can be associated with IBC, as presented later. Table 2 shows the voltage gains of each of the study rectifier structures. Table 2. Voltage gain of each rectifier Cells Voltage gain half-wave voltage doubler rectifier half-wave voltage triplicator rectifier full-wave voltage doubler rectifier full-wave CW voltage multiplier rectifier – CW Fig. 6Open in figure viewerPowerPoint Voltage multiplier rectifiers cells (a) Half-wave voltage doubler rectifier, (b) Half-wave voltage triplicator rectifier, (c) Full-wave voltage doubler rectifier, (d) Full-wave voltage CW voltage multiplier rectifier 2.2 Proposed high step-up topologies Four high-voltage gain DC–DC converters built on the IBC are proposed (Fig. 7). In the input cell of the IBC, the SI (Fig. 2a) is associated with the IBC, which generates the IBC with the SI (IBC-SI), as shown in Fig. 7a. Another arrangement is shown in Fig. 7b, where the IBC is combined with the mixed cell, as shown in Fig. 2b, of the SISL. This combination creates an IBC with SISL (IBC-SISL) – see Fig. 7b. One more arrangement is given in Fig. 7c, where the IBC is combined with the R2P2 cell. The generated converter, as shown in Fig. 7c, is denominated IBC with R2P2 (IBC-R2P2) cell. Finally, in the output port of the IBC, the full-wave CW voltage multiplier rectifier (CW), as shown in Fig. 6d, is combined with the IBC. Then, the IBC with a full-wave CW voltage multiplier rectifier (IBC-CW) is generated (Fig. 7d). As can be seen, m = 4 was chosen for the proposed converter of Fig. 7d, so that all converters could have approximately the same number of diodes. The inductors (L1 and L1#) of the IBC were replaced by the cells of Fig. 6. In addition, another strategy is the option to change the rectifier, as shown in Fig. 7d. These features allow the voltage gain factor of these cells to be incremented in the IBC, making the proposed converters achieve a high step-up. Each of these cells has its features, such as current stress, which implies conduction losses; voltage stress, which implies the intrinsic resistances of the components; component size, which implies the cost and volume of the converters (Table 3). Table 3. Converter specifications Specifications Value Specifications Value input voltage, Vi 30 V voltage gain, M 13.33 output voltage, Vo 400 V output power, Po 200 W switching frequency, fs 48 kHz — — Fig. 7Open in figure viewerPowerPoint Proposed high step-up DC–DC converter (a) IBC-SI, (b) IBC-SISL, (c) IBC-R2P2, (d) IBC-CW Note that all converters shown in Fig. 7 are proposed in this paper. Only the IBC had been previously proposed in the literature. Therefore, this family of five high-voltage gain DC–DC converters will be evaluated theoretically and experimentally in the following sections with the aim of verifying the advantages and disadvantages of each converter and each cell. It should be also noted that the components with the '#' symbol are identical to the components without this symbol. Thus, in the next analysis, when the component without the symbol is represented, this same analysis also applies to the element with the symbol '#'. 3 Theoretical comparative evaluation of the high-voltage DC–DC converters To infer a complete quantitative and qualitative study of the converters generated in and presented in the CCM, in the previous sections, the following aspects will be analysed: principle of operation; voltage gain derivation of the topologies; voltage and current stresses; component stress factor (CSF) and component count; converter estimated losses and efficiencies; and power density and relative cost. These features are taking into account that all power devices are ideal; the voltages of the capacitors are constant during one switching period so they are large enough; the N of the transformer is equal to . 3.1 Principle of operation All converters of the family have four operation stages. In the first and the third stages, the switches S1 and S2 are turned ON and all inductors are magnetised. In the second stage, S1 remains ON and S2 is turned OFF. The inductors connected in the switch S1 are magnetised and the inductors connected in the switch S2 are demagnetised. Finally, in the fourth stage, S1 is turned OFF and S2 is turned ON. In this stage, the inductors connected in switches S1 and S2 are demagnetised and magnetised, respectively. For more details, Table 4 summarises the operation stages of the semiconductors of each converter and Fig. 8 shows the key waveforms of all converters (Fig. 9). Table 4. Summary of the operation mode of converters Converters S1 S2 D1 D2 D3 Do1 Do3 Do2 Do4 IBC ON ON — — — OFF OFF ON OFF — — — OFF ON OFF ON — — — ON OFF IBC-SI ON ON ON OFF ON OFF OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF IBC-SISL ON ON ON — ON OFF OFF ON OFF ON — ON OFF ON OFF ON OFF — OFF ON OFF IBC-R2P2 ON ON — OFF ON OFF OFF ON OFF — OFF ON OFF ON OFF ON — ON OFF ON OFF IBC-CW ON ON — — — OFF OFF ON OFF — — — OFF ON OFF ON — — — ON OFF Fig. 8Open in figure viewerPowerPoint Key waveforms of converters Fig. 9Open in figure viewerPowerPoint Static voltage gain (a) Duty cycle versus voltage gain for N = 1, (b) Duty cycle versus turns ratio for M = 13.33 3.2 Static voltage gain versus duty cycle The voltage gain for the family of the converters is obtained by calculating the volt-second balance of its inductances, given in Table 5. As can be seen, each cell provides different features in the voltage gain when compared to the IBC. To illustrate the performance of each converter, Fig. 6a shows the M versus D plot for turns ratio of N = 1. The IBC-R2P2 has the highest voltage gain for all D range, when compared to the other converters. For M = 13.33, Fig. 6b shows the N of the transformer versus D. It can be noted that D is inversely proportional to N. To achieve the voltage gain M = 13.33, the D value of the switches and the N value of the transformer of each converter adopted in this paper are given in Table 6. Table 5. Static voltage gain Converters Static voltage gain IBC IBC-SI IBC-SISL IBC-R2P2 IBC-CW The factors MSI, MSISL, and MCW are given in Tables 1 and 2. Table 6. Duty cycle and turns ratio of each converter IBC IBC-SI IBC-SISL IBC-R2P2 IBC-CW D 0.51 N 3.26 2.18 1.63 1.63 1.63 3.3 Voltage stress across the semiconductor The maximum voltage for the device defines maximum limits of the voltage at which semiconductors can operate. Then, the semiconductor voltage stresses were calculated. Table 7 shows the voltage stresses and the total stress voltage factor of the semiconductors. Table 7. Absolute maximum voltage ratings for semiconductors IBC IBC-SI IBC-SISL IBC-R2P2 IBC-CW S D1 — — — D2 — — — D3 — — Do1 Do2, Do3 Do4 TVSS 4.08Vi 6.16Vi 8.16Vi 8.33Vi 4.08Vi TVDS 26.66Vi 32.91Vi 34.82Vi 34.82Vi 26.28Vi For the switch and the diodes, the total voltage stress values (TVSS) (TVDS), respectively, are the sums of the voltage stresses given by (3) and (4), respectively, (3) (4)where SVS and SVD are the maximum voltage stress values on the switch and diodes, respectively. The TVSS and TVDS depend on the converter input voltage (Vi), turns ratio (N) and duty cycle (D). Since N and D are defined in Table 7 for each converter, the total voltage stress on the switches and diodes can be calculated. As can be seen, the IBC-CW has lower voltage stress in the semiconductors. This feature is important to choose a MOSFET and diode with lower intrinsic resistance and low voltage drop. 3.4 Current stress evaluation of components The total stress current factors for the components of the converters are shown in Table 8. The total current stress of the switches (TCSS) is the sum of the stresses across each switch, which is given by (5); diodes (TCDS) is the sum of the stresses across each diode, which is given by (6); magnetics (TCWS) is the sum of the stresses across each winding, which is given by (7); capacitors (TCCS) is the sum of the stresses across each capacitor, which is given by (8) (5) (6) (7) (8)The TCS of the converters comprises the input current (Ii), inductor ripple () and duty cycle. In general, it can be said that a reduction of current stress on the devices may result in a decrease in their power losses. As can be seen, the IBC has lower current stress in the components. Table 8. Absolute maximum current ratings for components RMS current IBC IBC-SI IBC-SISL S1 S2 D1 — D2 — — D3 — Do1 Do2 Do3 Do4 L1 L2 — N1 N2 C1 — — — C2 — — Co1 Co2 Co3 Co4 TCSS 1.43Ii 1.43Ii 1.74Ii TCDS 0.22Ii 1.75Ii 1.41Ii TCWS 1.67Ii 1.75Ii 1.35Ii TCCS 0.15Ii 0.15Ii 0.42Ii RMS current IBC-R²P² IBC-CW S1 S2 D1 — — D2 — D3 — Do1 Do2 Do3 Do4 L1 L2 — N1 N2 C1 — C2 — — Co1 Co2 Co3 Co4 TCSS 1.43Ii 1.43Ii TCDS 0.64Ii 0.42Ii TCWS 2.08Ii 1.82Ii TCCS 0.65Ii 0.30Ii Where Δt = t1−t0 = t3−t2. 3.5 CSF and number of components For the processes, the weight of volt-ampere stress for each component of each converter and the total CSF were evaluated. The total CSF for the converter is the sum of the CSF of each component device. This analysis can recognise the limits of each converter for relative efficiency and size. For each converter, the CSF analysis will be determined for switches (SSCSF) given by (9); diodes (SDCSF) given by (10); magnetic devices (WCSF) given by (11); and capacitors (CCSF) given by (12) (9) (10) (11) (12)Based on the converters operation specifications summarised in Tables 3 and 6, the results of (9)–(12) are given in Table 9. Also, the component count for each type of CSF is shown aside. In general, it can be noted that the IBC has smaller values for each CSF type. This way, it can be concluded that this converter has a lower overall effort on the components. Table 9. Total component stress factors and component count CSF (component count) IBC IBC-SI IBC-SISL IBC-R2P2 IBC-CW total SSCSF (switch count) 2.91 (2) 4.41 (2) 7.09 (2) 5.95 (2) 2.91 (2) total SDCSF (diode count) 1.43 (2) 6.71 (8) 4.32 (6) 2.27 (6) 2.77 (4) total WCSF (winding count) 3.08 (4) 4.14 (6) 3.57 (6) 2.55 (6) 3.06 (4) total CCSF (capacitors count) 1 (2) 1 (2) 1.27 (4) 1.06 (4) 1 (4) sum of CSF (sum of comp.counts) 8.42 (10) 16.26 (18) 16.25 (18) 11.83 (18) 9.74 (14) 3.6 Converter estimated losses and efficiencies The converter operation specifications are given in Tables 3 and 6, the components of each converter are designed according to the methodologies described in the textbook [32]. Then, the converter parameters are given in Table 10. Table 10. Parameters of converters Parameters IBC IBC-SI IBC-SISL IBC-R2P2 IBC-CW MOSFET IRFP4668PbF (200 V, 130 A, 8 mΩ) diodes D1, D2, D3, D4, Do1, Do2 NTST30100CT (100 V, 30 A, 0.13 Ω) MBR40250 (250 V, 40 A, 0.22 Ω) C4D20120A (1200 V, 26 A, 0.74 Ω) inductors L1 L2 318 µH (78192bb Core Magnetic Core Material Magnetics® [30]. 54 mΩ) 380 µH (77071bb Core Magnetic Core Material Magnetics® [30]. 69 mΩ) 795 µH (77071bb Core Magnetic Core Material Magnetics® [30]. 130 mΩ) 634 µH (77071bb Core Magnetic Core Material Magnetics® [30]. 105 mΩ) 928 µH (77083bb Core Magnetic Core Material Magnetics® [30]. 76 mΩ) 318 µH (78192bb Core Magnetic Core Material Magnetics® [30]. 54 mΩ) transformer N1:N2 10:35 (MMT520T30.20.10B bb Core Magnetic Core Material Magnetics® [30].48 mΩ:171 mΩ) 15:35 (MMT520T30.20.10B bb Core Magnetic Core Material Magnetics® [30].72 mΩ:163 mΩ) 18:30 (MMT520T30.20.10B bb Core Magnetic Core Material Magnetics® [30].86 mΩ:137 mΩ) 18:30 (MMT520T30.20.10B bb Core Magnetic Core Material Magnetics® [30].86 mΩ:137 mΩ) 10:17 (MMT520T30.20.10B bb Core Magnetic Core Material Magnetics® [30].48 mΩ:93 mΩ) capacitors 9 µF (0.15 Ω) a Core Nanocrystalline Core Material Magmatec®.MMT520T30.20.10B [29]. b Core Magnetic Core Material Magnetics® [30]. All magnetics wire is Litz 67 × AWG37. The switch losses are given the following equation: (13)where ton and toff, capacitive losses (Coss) and MOSFET on-state resistance RDS(on) are given in the datasheet (14)intrinsic resistance rD is given by the datasheet. For inductors and transformer magnetics, their losses can be characterised into core and copper losses, given by (15) and (16), respectively. Moreover, the effect leakage inductance (Lk) of the transformer is that, when the switches turn OFF the losses increase. This behaviour can be added as an additional transformer loss (15) (16)where manufacture core information [33, 34] give all factor. Finally, capacitor losses are given by the following equation: (17)where ESR is the measured resistance of the gth capacitor. The estimated efficiency is given by (18)Using the parameters given in Tables 3, 10 and 11 and the stresses of the components given in Table 8, the distribution of the losses is shown in Fig. 10. It can be noted that the estimated efficiency of all the converters is higher than 90%. As can be seen in Fig. 10a, the IBC has the second higher estimated efficiency (94.73%), with an estimated loss of 10.54 W. The IBC-SI has the lower estimated losses in the inductors (Fig. 10b), when compared to the other converters. As for switches and diodes losses, the IBC-SISL shows the higher losses among the converter, as shown in Fig. 10c. Finally, the IBC-R2P2 has higher estimated losses in the transformer, as can be seen in Fig. 10d. Fig. 10e shows that the IBC-CW has the highest estimated efficiency (95.53%), with an estimated loss of 8.93 W. Table 11. Converter power density and relative cost IBC IBC-SI IBC-SISL IBC-R2P2 IBC-CW , W/cm3 0.78 1.11 0.94 0.80 0.70 RC, $ 48.27 51.91 55.59 57.51 42.68 Fig. 10Open in figure viewerPowerPoint Power converter loss distribution and efficiencies (a) IBC, (b) IBC-SI, (c) IBC-SISL, (d) IBC-R2P2, (e) IBC-CW 3.7 Power density and relative cost Power density, , is defined in (19) as the division of the power output by the total volume, where the total volume is typically a factor of two more than the sum of the partial volumes (19)Initially, all topologies are operating under the specifications presented previously. The volumes of each converter are given in Fig. 11. The IBC shows the highest volumes (120 cm3). The minor volume of 84 cm3 was achieved for the IBC-SI. The for each converter is shown in Table 11. The highest was achieved by the IBC-SI with 1.11 W/cm3. Fig. 11Open in figure viewerPowerPoint Estimated volume (in cm3) of each converter The value of each component has been evaluated according to [31]. The switches IRFP4668PbF, the diodes C4D20120A and NTST30100CTG, have been chosen and their cost is US$5.64, US$8.03 and US$0.97, respectively. The toroidal magnetic cores 78192, 77,083 and 77,071 from Magnetics have been chosen to implement the inductors. Their cost is US$3.8, US$1.84 and US$2.08, respectively. For the nanocrystalline core MMT520T30.20.10B for the transformer, the cost is US$4.82. The film capacitor B32594/M2 used in the prototype costs US$1.84. In this way, the cost for each prototype has been calculated using the relative cost, as shown in Table 11. 4 Design consideration and experimental results To confirm the main features evaluated in this paper, all the family was constructed in the laboratory. The Digital Signal Processor TMS320F28335, the source E4360A from Agilent®; electronic load 3252A, the Tektronix® Encore MD03000 oscilloscope and the Yokogawa WT1800® power meter were used to evaluate the converters. 4.1 Design consideration Based on the current and voltage stresses on the semiconductors, it is possible to find the re
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