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Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

2020; Institute of Electrical and Electronics Engineers; Volume: 67; Issue: 7 Linguagem: Inglês

10.1109/tns.2020.2977874

1558-1578

Juan Carlos Fabero, Hortensia Mecha, Francisco J. Franco, Juan Antonio Clemente, Golnaz Korkian, Solenne Rey, B. Cheymol, Maud Baylac, G. Hubert, Raoul Velazco,

VLSI and Analog Circuit Testing

A sensitivity characterization of a Xilinx Artix-7 field programmable gate array (FPGA) against 14.2-MeV neutrons is presented. The content of the internal static random access memories (SRAMs) and flip-flops was downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, block RAM (BRAM), or flip-flops. Single bit upsets (SBUs) and multiple cell upsets (MCUs) with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUlti-Scales Single Event Phenomena Predictive Platform (MUSCA SEP3) was used to make assessment of actual environments and an improvement of single event upset (SEU) injection test is proposed.