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Analysis of an efficient interleaved ultra‐large gain DC–DC converter for DC microgrid applications

2020; Institution of Engineering and Technology; Volume: 13; Issue: 10 Linguagem: Inglês

10.1049/iet-pel.2019.1138

1755-4543

Naser Vosoughi Kurdkandi, Tohid Nouri,

Microgrid Control and Optimization

IET Power ElectronicsVolume 13, Issue 10 p. 2008-2018 Research ArticleFree Access Analysis of an efficient interleaved ultra-large gain DC–DC converter for DC microgrid applications Naser Vosoughi Kurdkandi, Naser Vosoughi Kurdkandi Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorTohid Nouri, Corresponding Author Tohid Nouri Thdnouri@gmail.com orcid.org/0000-0003-1899-9097 Department of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, IranSearch for more papers by this author Naser Vosoughi Kurdkandi, Naser Vosoughi Kurdkandi Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorTohid Nouri, Corresponding Author Tohid Nouri Thdnouri@gmail.com orcid.org/0000-0003-1899-9097 Department of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, IranSearch for more papers by this author First published: 01 August 2020 https://doi.org/10.1049/iet-pel.2019.1138Citations: 4AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinked InRedditWechat Abstract This study deals with steady-state analysis and control of a step-up interleaved winding cross-coupled inductor DC–DC converter with high voltage gain and reduced voltage stress across semiconductors using voltage multiplier cells (VMCs). Because of the interleaved scheme, the thermal stress is reduced and the input current ripple is minimised. The leakage energy is recycled by passive lossless clamp circuit to the output. Meanwhile, the voltage stress across the semiconductors is substantially low. Hence, MOSFETs with less ON-state resistances and diodes with a less forward voltage drop can be utilised that improves the circuit performance. The operation principle and the steady state are discussed. Small-signal modelling of the proposed converter is derived via state-space averaging technique and a dual loop controller for output voltage regulation is designed. The adopted strategy utilises a fast dynamical inner loop to control the input current and an outer loop for the output voltage regulation. Finally, a 1 kW prototype with 60 V–1 kV voltage conversion is fabricated and tested to probe the carried analysis. 1 Introduction A DC microgrid is a controllable network having its own distributed generation sources, loads and energy storage units. In comparison with AC microgrid, the DC microgrids have the advantages of reduced power conversion stages, decoupling from the supply frequency, and better integration of energy storage and distributed (renewable) energy sources such as photovoltaic (PV) and fuel cell (FC) with increased overall system efficiency at reduced costs and sizes [1]. Low voltage DC microgrids (e.g. 1 kV bus) that consist of both regular service loads and sensitive equipment are interesting for application in data centres, building, and grid-connected renewable energy systems. Therefore, the integration of low voltage renewable energy sources such as PV and FC (up to 50–60 V) to a DC microgrid system demands for ultra-large gain and high-efficiency DC–DC converter [2]. The simplest solution is the conventional boost converter. However, to achieve high voltage gains, the converter should be operated around unity duty cycle, which seriously degrades the conversion efficiency and limits control criteria. Also, more expensive semiconductors should be selected to tolerate high voltage stress. Some topologies based on the switched capacitor and coupled inductors have been proposed to overcome the disadvantages of the conventional boost converter [2-12]. These solutions realise high voltage gain at moderate duty cycles and the voltage stress across the semiconductors in decreased successfully. Despite the advantages of the mentioned solutions, the efficiency of the single switch converters degrades at high power levels and the semiconductors suffer from high current/thermal stress. Interleaved structures can overcome this phenomenon by the distribution of the input current between the phases and consequently decrease the conduction losses and increases the conversion efficiency at high current and high power applications [13-26]. Also, the input current ripple is minimised that maintains the life time of the renewable power sources. An efficient modular high voltage gain interleaved boost converter is proposed in [13] that integrates a forward energy-delivering circuit with a voltage-doubler for DC microgrid applications. More modules can be paralleled to increase the power level and the dynamic performance for higher powers. Built-in transformer voltage multiplier cell (VMC) technique is utilised in [14-16] to achieve high voltage gain with high power density. The direct energy transfer concept is employed to propose a family of non-isolated step-up interleaved converters making the turns ratio of a built-in transformer as another design parameter for obtaining higher gains. To improve current sharing performance, high step-up converters with winding cross-coupled inductors (WCCIs) have been presented in [17, 20]. High voltage gain, low voltage stress across power MOSFETs and reduced peak current ripple are the advantages of these converters. The converters in [21, 22] employ coupled inductor VMCs to achieve high voltage gain at moderate duty cycles. The interleaved boost converter and a voltage-double module are connected in series in the converter of [23]. The secondary sides of the coupled inductors are in interleaved series connection and shared by two voltage-double modules to handle the interleaved energy storage. An interleaved high step-up converter with a coupled inductor and built-in transformer is presented in [24] which gives a more flexible design by adding an extra degree of freedom for voltage gain extension. This paper proposes an ultra-large gain DC–DC converter with the following features: (i) Ultra-large voltage gain and minimised voltage stress. (ii) Low input current. (iii) The leakage energy is successfully recycled to the output by the passive clamp circuit, which avoids the large voltage spikes across MOSFETs and improves the conversion efficiency. (iv) The diodes are switched at zero current switching (ZCS) and the reverse current recovery problem is alleviated due to the leakage inductances. (v) Minimised input current ripple. This paper is organised as follows: in Section 2, the principle operation is discussed; in Section 3, the steady-state analyses are given, in Section 4, the design guidelines are listed; in Section 5, the control process is described; in Section 6, the performance comparison is given; Sections 7 and 8 deal with experimental verification and conclusion, respectively. 2 Proposed converter and principle of operation The circuit schematic of the proposed converter is shown in Fig. 1. and are the leakage inductances; and are the magnetising inductances; , , , and are the regenerative capacitors; , , and represent the output capacitors; and are the power MOSFETs; and are parasitic capacitors of MOSFETs; and are the clamp diodes. The turns ratio of coupled inductor N is equal to . There are two sets of three windings coupled inductors in the proposed converter. The primary windings of the coupled inductors have the same performance as the inductors in the conventional interleaved boost converter. The secondary winding couples with its primary winding in its phase and the tertiary winding couples to its primary and secondary windings in another phase. The second and third windings of the coupled inductors serve as DC voltage source and are inserted in series to the circuit with a stacked scheme that helps to reduce the voltage stress across the MOSFETs. The following assumptions are made to simplify the analyses: (i) The voltage of all capacitors is considered constant in one switching period. Fig. 1Open in figure viewerPowerPoint Circuit configuration of the proposed converter (ii) The components are ideal, except that the body capacitors of the MOSFETs are considered. Generally, the interleaved converters are favourable to work at duty cycles higher than 0.5. This is mainly due to this fact that at , the voltage gain is low and also input current ripple gets large, which can affect the input power sources such as PV and FC. Therefore the performance operation is performed for . The key waveforms and the equivalent circuits of the proposed converter are shown in Figs. 2 and 3, respectively. Due to the completely symmetrical interleaved structure, the operating modes I to V and VI to X are mutually symmetrical. Therefore, only the operating modes I to V are described. Fig. 2Open in figure viewerPowerPoint Key waveforms of the proposed converter Fig. 3Open in figure viewerPowerPoint Equivalent circuits of the proposed converter at CCM operation in half switching cycle (a) Mode I, (b) Mode II, (c) Mode IV, (d) Mode V (Mode III is omitted due to maximum subfigure limitation of the journal format) Mode I []: The equivalent circuit is shown in Fig. 3a. At , is turned-on. is discharged, rapidly. Due to leakage inductances, the currents through the windings of coupled inductors are decreased linearly and the reverse recovery problem of the diodes is alleviated. is increased rapidly and when it reaches to at , this mode is ended. Mode II []: Due to maximum subfigure limitation of the journal format the equivalent circuit at this mode is not presented. At , the current that flows through the , gets equal to . The current through the secondary and tertiary windings of coupled inductors are zero at this mode. MOSFETs and are in turn-on state and other semiconductors are in a turn-off state. Output capacitors provide energy for the load. The leakage and magnetising inductances are charged, linearly: (1)Mode III []: The equivalent circuit is shown in Fig. 3b. At , is turned off. The parasitic capacitor is rapidly charged by the current . Consequently, the drain–source voltage of () increases until it reaches to the plus threshold voltage of . The clamp diode begins to conduct at and this mode is ended (2)Mode IV []: The equivalent circuit is shown in Fig. 3c. is on and the voltage across the is clamped at . The leakage energy is recycled to the output. This mode ends at when the leakage energy is fully released (3) (4)Mode V []: The equivalent circuit is shown in Fig. 3d. At this mode is off and the energy of the is transferred to , and load . This mode ends at when is turned-on and the next half switching cycle begins. (5) 3 Steady-state analysis of the proposed converter Since the time duration of modes I, III, VI, VIII are significantly short, they are not considered in the analysis. Due to the symmetry of the proposed converter, we have (6) (7)where and are the average currents that flow through the magnetising inductances. The average value of current through the clamp diodes is equal to and the average current that flows through the other diodes is equal to . By equating the surfaces of red and purple closed lines in Fig. 2 (see ) to and , respectively, we have (8) (9)The voltage stress across during modes IV and V can be written as below: (10) (11)According to Fig. 2 and using (8) and (9), the voltage across the leakage inductors can be expressed as (12)Referring to the equivalent circuit of Fig. 3c, the following equations can be obtained in mode IV: (13) (14)The output voltage can be expressed as below: (15)Using (12)–(14), the following equations can be derived: (16) (17)The average voltage across is given by the following equation: (18)substituting (10), (11), (13) and (15) into (18), the voltage gain at continuous conduction mode (CCM) is obtained as (19)Considering ideal coupled inductors with zero value of the leakage inductance, the voltage gain is obtained as (20) (21) (22) 4 Design guidelines of the proposed converter 4.1 Design of coupled inductors is designed to ensure the proposed converter operates in CCM. can be obtained by (23)After specifying the duty cycle and the input voltage, the turns ratio of the coupled inductor should satisfy the following equation: (24)After designing the required value of for CCM operation, the value of can be obtained by (25)where is the maximum value of the current through magnetising inductance, is the maximum of the magnetic flux density and is the core cross-sectional area of the coupled inductors. Using (24), the value of is yield. 4.2 Selection of semiconductors The voltage stress across the MOSFETs and power diodes can be obtained from (20) and (21). Also, the RMS current of the semiconductors are as below: (26) (27) (28) 4.3 Selection of capacitors The capacitors are designed in such a way that their corresponding voltage ripple is limited to a specific value. By applying this principle, the value of the capacitors can be formulated as: (29) (30) (31)where , and are the voltage ripple across , and , respectively. 5 Small-signal modelling and controller design The state-space averaged model of the proposed converter is obtained under the following considerations: (1) power MOSFETs and diodes are ideal; (2) equivalent series resistances (ESRs) of coupled inductors and output capacitors of the proposed converter are neglected; (3) only one of the regenerative capacitors in each VMC is considered as state variable ( and ); (4) the ESR of the regenerative capacitors is considered ; (5) converter operates under CCM, and is in steady-state; (6) the leakage inductances are neglected; (7) charging and discharging intervals of the drain–source capacitance of the power switches are neglected; and (8) the input voltage is constant. Four intervals can be considered during one switching period. The small-signal model can be derived as follows. 5.1 State-space modelling Intervals I and III: When both of the power switches and are in ON-state; the state equations can be written as below according to the equivalent circuit of Fig. 3b (32)Interval II: When is in ON-state and is in OFF-state; the state equations can be written as below according to the equivalent circuit of Fig. 3c (33)Interval IV: When is in OFF-state and is in ON-state; state equations can be obtained by (due to symmetry of the operations, the equivalent circuit of this mode has not been shown in Fig. 3) (34) 5.2 State-space averaged model It is clear that the weighting factors for each of the four operation modes are (d − 1/2), (1 − d), (d − 1/2), and (1 − d) in sequence, respectively [14]. Hence, the state-space averaging technique can be served to combine the state equations of four modes into the state-space averaged equation in matrix form as (35)where , , . A (see (36)), B, and C are obtained by (36) (37) (38) 5.3 Introduction of perturbations and obtaining of a small-signal linearised model The perturbation is applied to the state variables and other quantities around the steady-state point in (35) as (39) By comparing the DC and AC quantities while neglecting the second-order terms, the small-signal model of the proposed converter can be obtained as (40)where (see (41)) and are below: (41) (42) 5.4 Controller design In this step, a closed-loop controller is developed for the proposed converter. The component specification is the given values in Table 1 for laboratory validation. The open-loop poles and zeros for the transfer functions of the duty cycle to input current and duty cycle to output voltage is shown in Fig. 4. The system is naturally stable due to left-half-plane poles. Right-half-plane zero can be observed in . Hence, conventional voltage mode control cannot realise sufficient dynamic performance due to narrow closed-loop bandwidth. By employing the current control mode, the zeros are placed in the left-half-plane and the dynamic performance will be significantly improved. Therefore, a dual-loop control system is designed for the proposed converter, which its block diagram is shown in Fig. 5. Table 1. Performance comparison of the proposed converter Topology Converter in [19] Converter in [24] Proposed converter active switches 2 2 2 diodes 6 6 8 number of magnetic cores 2 2 2 number of windings 6 7 6 number of capacitors 5 5 7 voltage gain () voltage stress of power MOSFETs () maximum voltage stress across diodes () Fig. 4Open in figure viewerPowerPoint Open-loop poles and zeros (a) , (b) Fig. 5Open in figure viewerPowerPoint Developed dual loop controller The outer loop provides the reference current for the inner loop. In the inner current control loop, TCi(s) is the transfer function of the PI controller, TM is the transfer function of the modulator, Tid(s) is the transfer function of the duty cycle to input current and the Hi(s) is the transfer function of the current sensor. In the outer voltage control loop, TCv(s) is the transfer function of the PI controller, Tvi(s) is the transfer function of the input current to the output voltage, and the Hv(s) is the transfer function of the voltage sensor. 5.4.1 Current loop control design Fig. 6a shows the block diagram of the inner current control loop. Input current is feedback to the controller with the gain of Hi(s). The output of the PI controller is compared with a sawtooth wave in the modulator to generate the gate pulses of the power MOSFETs. Fig. 6Open in figure viewerPowerPoint Control block diagrams and frequency responses of the proposed converter (a) Inner loop controller, (b) Frequency response of the compensated and uncompensated system for an inner current loop, (c) Outer loop controller, (d) Frequency response of the compensated and uncompensated system for outer voltage loop The PI controller parameters should be designed properly to realise the minimisation of steady-state error and relatively fast dynamic performance. From the state-space analysis, the transfer function of the is obtained as follows: (43) The gain of the modulator is selected as below: (44)By assuming the maximum input current as 25 A and the maximum limit of the output voltage controller at 2.5 V, the transfer function of the current feedback sensor is obtained as (45)The open-loop transfer function of the current control loop is (46)The parameters of the PI controller are designed to have a PM of 60° at the crossover frequency of 3.3 kHz, which gives and [25, 26]. The value of the time constant of the controller is . The frequency response of the uncompensated and compensated systems for current control loop is shown in Fig. 6b. It can be seen that the designed values for the PI controller realises the PM of 61° at the crossover frequency of 3.4 kHz and also the low-frequency gain is improved compared to that of uncompensated value. 5.4.2 Voltage loop control design Fig. 6c shows the block diagram of the inner current control loop. The outer voltage control loop regulates the output voltage by providing the reference input current for the inner control loop. The cross over frequencies of the outer and inner control loops are sufficiently far apart from each other. Then the dynamic of the current control loop is neglected while designing the voltage control loop. The transfer function of the input current to the output voltage is given in (47). The voltage reference in the processor is set as 2.7 V. Then, the transfer function of the voltage sensor is selected as (47) (48)The open-loop transfer function of the voltage control loop is (49)The parameters of the PI controller are designed to have a PM of 60° at the chosen crossover frequency of 40 Hz, which gives and . The value of the time constant of the controller is . The frequency response of the uncompensated and compensated systems for current control loop is shown in Fig. 6d. It can be seen that the designed values for the PI controller realises the PM of 62° at the crossover frequency of 43 Hz and also the low-frequency gain is improved compared to that of uncompensated value. 6 Performance comparison In order to clearly demonstrate the advantages of the proposed converter, a comparison has been made between the proposed converter and converters published in [19, 24] in Table 1. The presented competitors in the references are favourable for DC microgrids and other applications such as high step-up high power conversion. Unfortunately, the proposed converter has two more diodes and capacitors. Fig. 7 shows the comparison of the voltage gain and voltage stress across the switching devices. The proposed converter has the highest voltage conversion ratio and the lowest voltage stress across MOSFETs and diodes. Then semiconductors with low ON-state resistances and low forward voltage drops can be adopted and the conversion efficiency can be maintained at a reasonable level. Accordingly, having two more diodes and capacitor can be covered by the advantages of the proposed converter. Hence, the proposed converter is a suitable candidate for the integration of renewable sources to DC microgrids. Fig. 7Open in figure viewerPowerPoint Performance comparison (a) Voltage gain, (b) Normalised voltage stress 7 Simulation and experimental verification Simulation results of the proposed converter in PSCAD-EMTDC along with the experimental results of a fabricated prototype circuit (Fig. 8) are presented to demonstrate the performance operation and the specifications of the converter are shown in Table 2. Figs. 9 and 10 show the simulation and experimental steady-state measured voltage and current of the proposed converter under full load, respectively. To fully probe the carried steady-state analysis, these measurements have been done with a nominal duty cycle of 60%. Table 2. Circuit specification of the proposed converter Components Specifications power 1 kW input–output voltage 60–970 V switching frequency 33 kHz regenerative capacitors output capacitors power MOSFETS/diodes /MUR1560 coupled inductors Fig. 8Open in figure viewerPowerPoint Photograph of hardware set-up Fig. 9Open in figure viewerPowerPoint Simulation and experimental voltage measurement of the proposed converter under full load (a) Voltages of the Co1, Co2 and Co3, (b) Voltages of MOSFET S1 and diode DC1, (c) Voltages of diodes Do1 and Dr11 Fig. 10Open in figure viewerPowerPoint Simulation and experimental current measurement of the proposed converter under full load (a) Currents of leakage inductances, (b) Currents of MOSFET S1 and diode DC1, (c) Currents of diodes Do1 and Dr11 According to (14), (16), (17) and (19), with this value of duty cycle, , , , are obtained. Fig. 9a shows the simulation and experimental results of the output capacitors’ voltages, that match to the steady-state analysis. Figs. 9b and c show the simulation and experimental voltage measurements across the power semiconductors. As can be seen, the voltage stress is substantially lower than the output voltage. Figs. 10a and b show the simulation and experimental current waveforms of , , and . The leakage energy transfers to the clamp capacitor when the MOSFET turns off and then recovers to the output. Fig. 10c shows the simulation and experimental current waveforms of and . The reverse-recovery problem is alleviated dramatically by the leakage inductance; so the reverse-recovery losses are reduced greatly and the EMI noise is suppressed, significantly. In order to verify the developed controller scheme, it is implemented in the Beaglebone Black processor by Texas Instrument. The dynamic response of the proposed converter for the load variation between 500 W and 1 kW is shown in Fig. 11. It can be seen that the voltage is well regulated at its reference value. Fig. 11Open in figure viewerPowerPoint Dynamic response of the proposed converter between 1 kW and 500 W Table 3 shows the measured efficiency of the proposed converter under different output power. As can be seen, the maximum efficiency is about 96.1% that is occurred at and the full load conversion efficiency is about 94.6%. Table 3. Measured efficiency of the proposed converter Po, W 200 300 400 500 600 700 800 900 1000 efficiency, % 94.1 94.5 95.2 96 96.1 95.9 95.8 95 94.6 8 Conclusion The steady-state analysis, small-signal modelling and control of a high step-up DC–DC converter have been proposed in this paper. The proposed converter has the advantages of high voltage gain, low voltage stress across power switches and minimised input current ripple. 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