Portal de Periódicos da CAPES

Effect of Gate-Oxide Degradation on Electrical Parameters of Silicon Carbide MOSFETs

2020; Institute of Electrical and Electronics Engineers; Volume: 67; Issue: 6 Linguagem: Inglês

10.1109/ted.2020.2990128

1557-9646

Ujjwal Karki, Nomar S. Gonzalez-Santini, Fang Zheng Peng,

Advancements in Semiconductor Devices and Circuit Design

Although gate-oxide degradation occurs in both silicon (Si) and silicon carbide (SiC) MOSFETs, it requires a special attention in SiC MOSFETs. This is because the gate oxide in SiC MOSFETs is comparatively thinner than the gate oxide in Si MOSFETs, and thus, a higher electric field that appears across it could push the gate oxide to its reliability limit. While several electrical parameters have been identified as precursors (indicators) for monitoring the gate-oxide degradation process in Si MOSFETs, very few have been identified for their SiC counterparts. The purpose of this article is twofold. The first objective is to demonstrate that the three gate-oxide degradation precursors identified for Si MOSFETs: 1) threshold voltage, 2) gate-plateau voltage, and 3) gate-plateau time can also be extended to SiC MOSFETs. The second objective is to demonstrate analytically and experimentally that all three precursors increase in a linear-with-log-stress-time manner during gate-oxide degradation in both planar and trench-gate SiC MOSFETs. The increasing trends of precursors and their associated logarithmic time responses were experimentally verified by inducing accelerated gate-oxide degradation in two different commercial SiC MOSFETs (650-V, 70-A trench-gate MOSFETs and 1200-V, 19-A planar MOSFETs) under high temperatures of 150 and 125 °C, respectively.