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An Efficient Optimization and Secured Triple Data Encryption Standard Using Enhanced Key Scheduling Algorithm

2020; Elsevier BV; Volume: 171; Linguagem: Inglês

10.1016/j.procs.2020.04.113

1877-0509

Akshitha Vuppala, Rishu Roshan, Shaik Nawaz, J. V. R. Ravindra,

Coding theory and cryptography

As a result of advancement in technology, the transfer rate of digital data through cryptographic embedded devices such as smart cards is increasing rapidly and these devices are vulnerable to attacks. Cryptography provides various algorithms to secure the data. Triple Data Encryption Standard (Triple-DES) algorithm [1] is one such and uses the Data Encryption Standard (DES) block thrice this reinforces the key size to 192 bits. The reliability of data can be made progressive by procuring the keys. In Triple-DES, the key generation does not undergo encryption, making the job of the cryptanalyst easy. A strategy must be followed to make the keys more reliable and avoid the glitches in the power traces to make it more strenuous for them. To satisfy the above requirement FORTIS algorithm has been proposed for generation of sub-keys and investigates the strength of the algorithm against side-channel power attacks using ChipWhisperer®-Lite and Artix FPGA as target board. The number of glitches that represent the leakage power are approximately reduced by 53.3% and from the power traces of key schedule algorithm it is seen that all the instructions being performed are similar, so it becomes difficult to identify which operation is being performed and the probability of guessing entropy has been reduced in 86.6% of the cases.