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Revisado por pares
Switching losses prediction methods oriented to power MOSFETs – a review
2020; Institution of Engineering and Technology; Volume: 13; Issue: 14 Linguagem: Inglês
10.1049/iet-pel.2019.1003
ISSN1755-4543
AutoresWesley Josias de Paula, Gabriel H. M. Tavares, Guilherme M. Soares, Pedro S. Almeida, Henrique A. C. Braga,
Tópico(s)Semiconductor materials and devices
ResumoIET Power ElectronicsVolume 13, Issue 14 p. 2960-2970 Review Article Free Access Switching losses prediction methods oriented to power MOSFETs – a review Wesley Josias de Paula, Corresponding Author wjpeletrica@yahoo.com.br orcid.org/0000-0003-2260-4721 Electrical Engineering Post-Graduation Programme, Federal University of Juiz de Fora, Rua José Lourenço Kelmer, s/n – São Pedro, Juiz de Fora, MG, BrazilSearch for more papers by this authorGabriel Henrique Monteiro Tavares, Electrical Engineering Post-Graduation Programme, Federal University of Juiz de Fora, Rua José Lourenço Kelmer, s/n – São Pedro, Juiz de Fora, MG, BrazilSearch for more papers by this authorGuilherme Marcio Soares, Electrical Engineering Post-Graduation Programme, Federal University of Juiz de Fora, Rua José Lourenço Kelmer, s/n – São Pedro, Juiz de Fora, MG, BrazilSearch for more papers by this authorPedro Santos Almeida, orcid.org/0000-0002-1919-0671 Electrical Engineering Post-Graduation Programme, Federal University of Juiz de Fora, Rua José Lourenço Kelmer, s/n – São Pedro, Juiz de Fora, MG, BrazilSearch for more papers by this authorHenrique Antonio Carvalho Braga, Electrical Engineering Post-Graduation Programme, Federal University of Juiz de Fora, Rua José Lourenço Kelmer, s/n – São Pedro, Juiz de Fora, MG, BrazilSearch for more papers by this author Wesley Josias de Paula, Corresponding Author wjpeletrica@yahoo.com.br orcid.org/0000-0003-2260-4721 Electrical Engineering Post-Graduation Programme, Federal University of Juiz de Fora, Rua José Lourenço Kelmer, s/n – São Pedro, Juiz de Fora, MG, BrazilSearch for more papers by this authorGabriel Henrique Monteiro Tavares, Electrical Engineering Post-Graduation Programme, Federal University of Juiz de Fora, Rua José Lourenço Kelmer, s/n – São Pedro, Juiz de Fora, MG, BrazilSearch for more papers by this authorGuilherme Marcio Soares, Electrical Engineering Post-Graduation Programme, Federal University of Juiz de Fora, Rua José Lourenço Kelmer, s/n – São Pedro, Juiz de Fora, MG, BrazilSearch for more papers by this authorPedro Santos Almeida, orcid.org/0000-0002-1919-0671 Electrical Engineering Post-Graduation Programme, Federal University of Juiz de Fora, Rua José Lourenço Kelmer, s/n – São Pedro, Juiz de Fora, MG, BrazilSearch for more papers by this authorHenrique Antonio Carvalho Braga, Electrical Engineering Post-Graduation Programme, Federal University of Juiz de Fora, Rua José Lourenço Kelmer, s/n – São Pedro, Juiz de Fora, MG, BrazilSearch for more papers by this author First published: 01 November 2020 https://doi.org/10.1049/iet-pel.2019.1003 AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinked InRedditWechat Abstract The aim of this study is to review the state-of-the-art of recent prediction methods for power metal-oxide-semiconductor field-effect transistors (MOSFETs) switching losses using datasheet parameters. A detailed technical literature investigation is carried out to collect the latest research contributions on this subject, pointing out their main features and drawbacks. Then, a particular section is dedicated to compare three different selected methods oriented to Si-based and SiC-based MOS power transistors. This analysis is performed on several voltage and current level ratings using an experimental prototype of a double pulse circuit. According to the experimental-supported study included here, at a particular volt–ampere condition, the Ahmed method provided the lowest theoretical error of 2.38%, while the Guo method attained 41.2% and Brown method presented 28.5%. In addition, according to the experimental results it can be concluded that it is very difficult to obtain a high level of accuracy concerning MOSFET switching losses, mainly due to the uncertainty when selecting datasheet information. Among the parameters that most influence the measurements, one could list the MOSFET transconductance, the channel threshold voltage and the parasitic inductances. Nomenclature diode capacitance [F] time interval used to achieve transistor test current [s] time interval used to measure turn-on losses [s] time interval used to measure turn-off losses [s] times intervals related to the Guo's method [s] bypass capacitor [F] drain-source capacitance [F] gate-drain capacitance [F] gate-source capacitance [F] input capacitance [F] output capacitance [F] reverse transfer capacitance [F] instantaneous energy [J] turn-off energy switching losses [J] turn-on energy switching losses [J] total energy switching losses [J] switching frequency [Hz] MOSFET transconductance [S] load current [A] drain current [A] gate current [A] load inductor current [A] load inductor [H] drain stray inductance [H] gate inductance [H] source stray inductance [H] P instantaneous power [W] power MOSFET switching losses [W] total gate charge [C] on-resistance of the MOSFET [Ω] internal gate resistance [Ω] external gate resistance [Ω] total gate resistance [Ω] equivalent series resistance of the power loop [Ω] time intervals related to the Brown's method [s] voltage Fall time related to the Guo's Method [s] time taken for the voltage to fall to its on-state value during the turn-on transient [s] time for the drain current to reach its off-state value [s] time taken for the current to rise to its on-state value [s] MOSFET junction temperature [°C] total time for the turn-off [s] total time for the turn-on transient of the MOSFET [s] voltage rise time related to the Guo's method [s] time required for drain-to-source voltage to achieve its nominal value [s] switching period [s] Schottky diode voltage [V] input voltage [V] high-level output voltage applied to the external resistance [V] voltage driver [V] drain-source voltage [V] forward voltage of [V] gate-drain voltage [V] low-level for turn-off the MOSFET [V] high-level for turn-on the MOSFET [V] gate-source voltage [V] miller plateau voltage [F] channel threshold voltage 1 Introduction Currently, the silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET) is the preferred semiconductor device in low to medium-powered high-frequency power processing applications [1-5]. This kind of transistor represents one of the major sources of power losses and heating in such applications often requiring a proper cooling system to be integrated into the static converter. According to the tendency of higher switching frequencies of such converters, device switching losses need to be very well modelled in order to achieve a good quality design [6]. Loss modelling methods can be categorised into three main types for these devices, starting with the simplest analytical models, SPICE-based models and then moving to the more complex physical-modelling realm [7]. The estimation or calculation of the switching losses in power MOSFETs has been a major matter of investigation in the technical literature, although it is not yet a consolidated subject, mainly because of the inaccuracy or complexity of some methods. This topic is important because a more accurate assessment regarding such losses may reduce the design and optimisation time of a power converter without the need to build various prototypes for experimental comparison [8]. Considering that the analytical methods of switching losses usually present low accuracy, several works have been proposed in the technical literature to improve the key issues on the matter, namely simulation time, computational effort and accuracy [9, 10]. In this sense, the main objective of this paper is to present a review of the most recent datasheet-dependent switching losses prediction methods oriented to power MOSFETs. A performance comparison is done, concerning three methods and employing an experimental double-pulse test (DPT) approach to gather the experimental data. This paper is structured as follows: Section 2 discusses some conventional estimation methods for power MOSFETs switching losses and addresses their main limitations. Section 3 presents an extensive comparison involving three different analytical techniques devised to estimate the switching losses more precisely. To effectively evaluate the main features and performance of these techniques, an experimental setup is proposed. Thus, Section 4 is dedicated to describe the data acquisition methodology, which is applied to three different power MOSFET devices, including one SiC FET. A thorough discussion regarding the results is given at the end of this section, and then the main conclusions are compiled in Section 5. 2 Switching losses estimation in power MOSFET Power losses analysis approaches are presented as an interesting alternative for the performance investigation of power MOSFETs devices. This research field evaluates both the conduction losses and the switching losses. The first one is related to the power losses in the device on-resistance whereas the former results of a simultaneous exposure of a MOSFET to voltage and current during a transition between conducting and blocking states. This paper is focused on switching losses estimation methods and, according to the technical literature, such approaches are devised to obtain shorter simulation times and higher accuracies. These prediction models can be particularly divided into three categories: (i) Physical-based model: These models are based on semiconductor physics, such as the thickness of oxide layer, substrate doping concentrations, device geometry, and so on. The description of electrical and thermal behaviour is obtained by solving equations related to the physical behaviour of the device with some simplifications. (ii) SPICE-based model: Such models are partly based on device physics also including concentration density values, oxide thickness and even junction temperature. In many cases and seeking for simplicity, the standard low voltage device models must be adapted to address high-voltage power device modelling, which can lead to the loss of the physical meaning regarding some parameters and equations. (iii) Mathematical model (analytical model): Which adopts expressions by means of the equivalent circuit analysis. Their relevant model parameters have no direct physical meaning. The main advantage of this approach over the aforementioned models is the lower simulation time and simple implementation. However, the biggest challenge of this alternative is the parameter dependency and accuracy. At following a deeper discussion about the methods cited in the last paragraphs is given: physics-based model, SPICE-based model, and analytical model. Physical models usually adopt an advanced multidimensional device simulator, such as Sentaurus, Technology Computer-aided Design (TCAD) etc. In [11, 12], a physical-based model of the MOSFET device is simulated using the TCAD numerical tool, combined with an external circuit developed in SPICE to model the switching transients. These models can provide very accurate results, but they are very complicated, computationally intensive, and require detailed information on physical material properties and not very suitable for circuit simulation, in addition, as reported in [13], it may take few days to simulate a complete static converter. Thus, they are more likely to be used by engineers for optimisation and device development. The SPICE-based model typically involves the device characterisation through experimental evaluation along with numerical simulations of a generic device. Most models are either excessively complex or do not incorporate the required stray elements into the device modelling, thus producing inaccurate switching waveforms. In [14], a model oriented to Si and SiC power MOSFET devices was proposed, with a tool for extracting parameters from the datasheet that can be applied to both technologies (Si and SiC). However, depending on the application, this model may turn out to be too complex for fast circuit simulation [14]. In [15], a behavioural SPICE model is presented, in which various parameters, such as device transconductance and threshold voltage, are evaluated. In addition, their model considers the non-linear gate-drain capacitance, but it did not examine the influences of drain and source stray inductances. In another work [16], an enhanced method considering the effect of turn-off gate voltage is shown, improving on previous ideas. Further improvement is made in the method proposed in [17], assuming the non-linearities in all of the capacitances. Nevertheless, these particular SPICE-based models are extremely complex due to the exponential behaviour of the gate-source voltage near-threshold condition, making it a slow method for quick evaluation on the performance of converters. Although SPICE-based models are faster than physical models, they also demand long simulation times when small time-steps are used, being a significant drawback in the evaluation of high-frequency converters. Despite that the SPICE models present a good trade-off between accuracy and simulation time, the fact that some parasitic elements are not properly modelled can lead to poor results in terms of switching losses prediction [9, 14, 15]. On the other hand, the analytical calculation of switching losses is a straightforward mechanism to obtain a first insight regarding the switching losses, thus allowing a quick comparison between different devices and operating conditions. The following points outline how parameters and conventional assumptions affect the accuracy of analytical-based predictions: (A1) MOSFET parasitic components (such as source inductance, drain inductance and MOSFET output capacitances): These parasitic parameters should be included as they are an important source of switching losses, and because they contribute to an overlap between the device voltage and current [7, 9, 13, 18-26]. (A2) Loss distributions: Since the charging and discharging losses cannot be separated, the effect of MOSFET output capacitance, , i.e. , while and are the gate-source and the gate-drain capacitances, respectively. It is indirect and affects both the rise and fall time intervals. The separation between the overlap loss and the losses owing to the MOSFET output capacitance results in inaccurate predictions. Moreover, using a constant fixed time for rise and fall intervals leads to an improper approximation [27]. (A3) Current divergence: The input characteristic obtained by means of MOSFET datasheets (gate charge, curve) cannot be easily used because it neglects the currents. In addition, this approach adopts an erroneous assumption that the load current is equal to the channel current. Therefore, such simplifications introduce current deviations when compared to the device actual behaviour [27]. It must be also highlighted that all the transition periods are determined from the parasitic capacitance values. (A4) Circuit analysis (double-pulse circuit, as detailed in Section 2.1): In the analytical approach it is considered the complete solution of the electrical circuit where the device is employed by including parasitic inductances and capacitances in all operating stages. The solution is carried out based on the effects of the parameters, such as gate driver voltage, switching frequency, transconductance, threshold voltage, gate source inductance etc. The highlighted point is that circuit parameters drive the rise time and fall time [27]. On the other hand, most of the literature uses the circuit parameters only in the circuit switching loss calculation of the rise and fall time intervals. Then, the circuit parameters effect variation is divided into two alternatives: (A4.1) Add the MOSFET characteristics and circuit parameters for calculating the turn-on and turn-off times; (A4.2) Add circuit parameters just to derive power losses under turn-on and turn-off intervals. Based on the aspects cited here, the classification for prediction of switching losses in power MOSFETs can be organised according to Fig. 1. As already mentioned, this paper proposes a discussion concerning the issues associated with switching losses prediction by analytical methods based on datasheet parameters only. Fig. 1Open in figure viewerPowerPoint Classification of switching losses estimation methods oriented to power MOSFETs Finally, it is important to highlight that many models are essentially similar for Si and SiC MOSFETs [15, 28, 29].The different characteristics of SiC-MOSFETs compared to Si-devices require some minor modelling adjusts to better represent their particularities and to avoid simulation inconsistencies. For example, the SiC-MOSFETs low on-resistance and fast switching response can cause significant ringing and higher voltage overshoots [30]. Furthermore, some works also present refinements based on experimental data for allowing the model to reproduce a specific SiC feature [30]. 2.1 Double pulse test circuit In the case of power MOSFET loss analysis, experimental validation can be performed with either calorimetric or electrical power losses measurement techniques. The calorimetric technique is used to measure the total losses of a given device during the continuous operation within an enclosed thermal chamber [31, 32]. Although this approach is useful for estimating the efficiency of the whole converter, there are some drawbacks when applying it to predict the losses of a single device. Typically, in the calorimetric technique, the gate driver is placed outside the thermal chamber. This tends to be detrimental to the switching performance, mainly in circuits with high dv/ dt like SiC and GaN-based devices, due to the insertion of parasitic elements that cause ringing and alter the switching behaviour [32]. These measurements will also include losses deriving from the freewheeling diode's reverse recovery current and other parasitic elements. Another negative factor lies in the need to perform some form of post-processing, to separate switching losses from conduction losses, which would be indeed very hard in a calorimetric set. In contrast to the calorimetric method, the purely electrical approach to loss measurement using a DPT circuit allows to separately compute the switching losses using current and voltage waveforms, which are obtained from an oscilloscope, without the need of an external post-processing system [31-33]. Fig. 2a depicts the test circuit and Fig. 2b the simplified theoretical electrical waveforms of the device under test, namely the drain-to-source voltage and drain current. Fig. 2Open in figure viewerPowerPoint Double pulse test (DPT) (a) Typical experimental circuit used to evaluate the switching losses of a given MOSFET (M) or DUT, (b) Simplified theoretical switching waveforms of a power MOSFET, adapted from [34] In Fig. 2a, , is the gate-source voltage, is the input voltage, is the drain current, is the average gate drive current, DUT an acronym for a device under test (highlighted in dashed lines), is freewheeling diode, is the load inductor and is the total gate resistance, given by (1) where is the internal gate resistance and is the external gate resistance. Fig. 3 shows the idealised waveforms of the DPT circuit. The first pulse duration is such that the current through device reaches the desired test value, . So, the falling edge of the first pulse provides information related to the turn-off power loss of the device. As a consequence, the pulse width, is defined by the combination of the load parameters and MOSFET characteristics as shown in Fig. 3 and (2). Moreover, the signal magnitude must be the same as the gate-source voltage recommended by the manufacturers in datasheets. For SiC devices, as an example, a value of 18 V is commonly adopted. Fig. 3Open in figure viewerPowerPoint Idealised waveforms of the DPT circuit In Fig. 3, is the high-level for turn-on the MOSFET and is the low-level for turn-off the MOSFET (2) where is the on-resistance of the MOSFET under test. Usually, the second pulse is recommended to be as short as possible, so that the current decreases according to a dimensionless value, which depends on . Thus, is defined by (3) where represents the forward voltage of . represents the maximum value that can achieve at this stage, as shown in (4). In addition, is a dimensionless value greater than zero and indicates how much the load current can increase regarding its original value. After this stage, the MOSFET is turned off. Usually, a time of 500 ns are adopted for and (4) According to this explanation, the experimental evaluation is taken at once and no repetition is conducted to avoid an increment of device junction temperature. A commonly used formula for estimating the power MOSFET switching losses () is given by (5) [7] (5) where frequency is the inverse of the switching period ; is the drain-to-source DUT voltage is the drain current of the MOSFET, while and are the total time for the turn-on and turn-off transient of the MOSFET, respectively. From (5), the first term simply calculates the switching power loss during the transition periods in Fig. 2b. The second term represents the losses owing to the output capacitance (), whose energy is dissipated in the device channel by means of a joule losses mechanism, during the entry into conduction stage. According to semiconductor manufacturers application notes, the switching times and are often estimated by (6) where is the average gate drive current. The classic estimation method is based on computing the switching losses by using the expression (5), which adopts the switching times derived by (6). However, this can be very inaccurate, mainly due to the controversial inclusion of the second term in (5), which is related to the output capacitance, and because of the non-linear nature of drain-to-source voltage. In addition, the extraction procedure of the gate charge parameter is usually not a trivial procedure considering the variety of commercially available products. Furthermore, the documentation adopted by the manufacturers does not follow the same guidelines. Basically, a thorough evaluation may consider some particularities and parameters, such as the influence of parasitic inductances, as well as the drain-to-source voltage dependence with the junction capacitances. Over the last few decades, many studies have been presented in the most prestigious scientific conferences and journals, highlighting the key importance of proper modelling of the MOSFET non-linear capacitance aiming a more accurate prediction of device switching losses, especially in hard switching converters. Various approaches to MOSFET modelling and parameters extraction have also been proposed [35-38]. Particularly, in [37, 38], the authors discuss an experimental test allowing the identification of additional parameters, with respect to datasheet information, providing more accurate MOSFET capacitances models for the analysis of switching transitions. Such parameters describe the area modulation effect of gate-source and drain-to-source voltages on the interelectrode capacitances during commutations. They are identified by means of empirical evaluations starting from experimental measurements during switching transitions. Recent research studies have investigated and proposed more accurate switching losses estimation. These works can be classified depending on the previously listed points, as organised in Table 1, which shows the switching prediction losses models highlighting the aspects that are considered and disregarded while quantifying such losses. As can be seen in Table 1, the authors of [18, 19, 22, 39] have proposed approaches for switching loss prediction that consider the changes in MOSFET behaviour during the transitions intervals, mainly the changes in parasitic capacitances. The aforementioned models allow for a straightforward and fast estimation of the switching losses by simplifying the calculation of time intervals and . However, their main drawback is that they neglect switching losses effects due to parasitic inductances. Typically, these models predict that turn-on and turn-off losses are nearly similar in magnitude. In a real converter, operating at high switching frequencies, those models reveal to be highly inaccurate since turn-off loss is much larger due to parasitic inductances [21]. In addition, current and voltage ringing are always observed in a switching-mode power supplies and it is ignored in the traditional model. It is interesting to note that [20], for example, takes into account the non-linear nature of device capacitances and the parasitic inductances of the circuit (such as the source inductance shared by the power stage and driver loop as well as the drain inductance). Table 1. Comparison of the mathematical switching power loss models Characteristic Prediction loss model [18] [13] [19] [22] [23] [24] [7] [25] [9] [26] [5] [20] [21] (A1) YESa YES YESa YESa YESa YESa YES YES YES YESa YES YES YES (A2) NO NO NO NO NO NO NO NO NO NO NO NO NO (A3) NO NO NO NO NO NO NO YES NO YESb YES YES YES (A4.1) NO NO NO YES NO NO YES NO NO NO NO NO NO (A4.2) YES YES NO NO YES YES NO YES YES YES YES YES YES a The method considers exclusively the stray capacitances. b The method considers variable resistance of the MOSFET gate driver. It is also worth mentioning that the model proposed by Eberle et al. [21] included the impact of power supply inductance and the transistor parasitic inductances on switching losses. The model uses simple equations to calculate the rise and fall times and piecewise linear approximations of voltage and current waveforms to allow switching losses calculation. According to this reference, the rise time is strongly related to the MOSFET parasitic capacitances and the current capability of the gating circuitry; the fall time is, on the other hand, dictated not only by the same parameters but also by the circuit parasitic inductances. In [5], a circuit-level analytical model also takes MOSFET parasitic capacitances and inductances, along with circuit stray inductances and reverse current of the freewheeling diode into consideration in order to evaluate the MOSFET switching characteristics. Graovac et al. [23] add the non-linear effect of the reverse transfer capacitance , i.e. for the calculation of voltage rise time and voltage fall time and adopts the two capacitance average value in calculation. This method considers the worst case for the switching losses prediction. As reported by Graovac et al. [23], regarding turn-on energy losses in power MOSFETs occurs when the influence of the reverse-recovery of the freewheeling diode is accounted. In Guo et al. [24], an improved calculation methodology of [23] is developed by using the datasheet reverse transfer capacitance () against drain-to-source voltage () curve provided in datasheet. The method improves the evaluation of the drain-to-source voltage during the rise-time voltage, and the fall-time voltage (). However, it still disregards the effects of parasitic inductance in the analysis. To overcome the limitations of most estimation methods mentioned before, some authors have addressed the dynamic behaviour of a power MOSFET in segmented divisions describing various commutation stages [7, 13, 25]. All these models have in common the segmentation in various time intervals of an operation cycle. In this context, the turn-on and turn-off periods are constituted by multiple intervals, each one associated with an equivalent circuit by switching an inductive load. It is claimed by some authors, e.g. Ren et al. [7], that including so many parasitic effects and physical parameters in analytical switching losses prediction methods is still advantageous since the simulation time remains much shorter than those associated to the so-called physical-parameter-based methods or even compared with SPICE-based simulations methods. Also, according to the authors, the resonances between parasitic inductances and capacitances can result in significant switching losses. To improve the accuracy of the analytical method, the inclusion of drain and gate inductances in the circuit is proposed in [13]. Those elements represent parasit
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