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Bridge‐type fault current limiter and hybrid breaker for HVDC grids applications

2020; Institution of Engineering and Technology; Volume: 14; Issue: 18 Linguagem: Inglês

10.1049/iet-gtd.2020.0013

1751-8695

Amir Heidary, Kumars Rouzbehi, Morteza Hesami, Mehdi Bigdeli, Carlos Bordons,

Superconductivity in MgB2 and Alloys

IET Generation, Transmission & DistributionVolume 14, Issue 18 p. 3913-3919 Research ArticleFree Access Bridge-type fault current limiter and hybrid breaker for HVDC grids applications Amir Heidary, Amir Heidary orcid.org/0000-0002-5265-4634 Department of Electrical Engineering, Zanjan Branch, Islamic Azad University, Zanjan, IranSearch for more papers by this authorKumars Rouzbehi, Corresponding Author Kumars Rouzbehi Krouzbehi@us.es orcid.org/0000-0002-3623-4840 Department of Systems Engineering and Automatic Control, University of Seville, Seville, SpainSearch for more papers by this authorMorteza Hesami, Morteza Hesami Department of Electrical Engineering, Zanjan Branch, Islamic Azad University, Zanjan, IranSearch for more papers by this authorMehdi Bigdeli, Mehdi Bigdeli orcid.org/0000-0003-3268-6230 Department of Electrical Engineering, Zanjan Branch, Islamic Azad University, Zanjan, IranSearch for more papers by this authorCarlos Bordons, Carlos Bordons Department of Systems Engineering and Automatic Control, University of Seville, Seville, SpainSearch for more papers by this author Amir Heidary, Amir Heidary orcid.org/0000-0002-5265-4634 Department of Electrical Engineering, Zanjan Branch, Islamic Azad University, Zanjan, IranSearch for more papers by this authorKumars Rouzbehi, Corresponding Author Kumars Rouzbehi Krouzbehi@us.es orcid.org/0000-0002-3623-4840 Department of Systems Engineering and Automatic Control, University of Seville, Seville, SpainSearch for more papers by this authorMorteza Hesami, Morteza Hesami Department of Electrical Engineering, Zanjan Branch, Islamic Azad University, Zanjan, IranSearch for more papers by this authorMehdi Bigdeli, Mehdi Bigdeli orcid.org/0000-0003-3268-6230 Department of Electrical Engineering, Zanjan Branch, Islamic Azad University, Zanjan, IranSearch for more papers by this authorCarlos Bordons, Carlos Bordons Department of Systems Engineering and Automatic Control, University of Seville, Seville, SpainSearch for more papers by this author First published: 09 July 2020 https://doi.org/10.1049/iet-gtd.2020.0013Citations: 5AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract The fast raising nature of DC fault currents and sensitivity of high-voltage DC (HVDC) power converters to DC faults is critical protection issues. On the other hand, DC fault current does not meet zero; which causes DC to fault current breaking process become more challenging. Specifically, to protect HVDC grids against DC fault currents, the development of very fast breakers is crucial. This study proposes a DC fault current limiter and breaker, which is able to protect the HVDC system/grid in a very fast and safe manner. The main goal of this study is to enhance the performance of already in the market hybrid DC circuit breakersincluding the magnitude of fault current and breaker operation speed. In the proposed HVDC fault current limiter and breaker, the fault current is limited in two stages by an inductive and resistive current limiter, which drastically decreases the main breaker dissipated energy. The functionality of the proposed HVDC fault current limiter and breaker is mathematically analysed, and then verified by PSCAD and Matlab/Simulink. Finally, simulation results are validated by scaled-down laboratory examinations. 1 Introduction The idea of supergrids for the purpose of energy management and marketing would be a promising solution with the development of overlaid high-voltage DC (HVDC) grids [1]. When a DC fault takes place, the relatively low impedance of the HVDC grid is the tremendous challenge, as fault penetration is much faster and deeper than in the case of AC grids [2]. Therefore, HVDC grids need to have appropriate breakers to interrupt damage-causing fault currents [3]. In recent years, several ideas for HVDC breaker schemes have been introduced. Active and passive resonant breakers were proposed as a solution to DC systems [4–6]. However, they are not fast enough to protect the voltage source converter (VSC)-based HVDC grid [4]. Three significant expected features of HVDC circuit breakers (CBs) are very fast-breaking action, minimum conduction losses, and the prevention of excessive overvoltage [4]. Hybrid HVDC breaker has introduced as a proper technology that is able to break high DC fault currents in a fast and reliable manner [7–12]. Conductive power losses of the hybrid breaker are very low because of using a solid-state load commutation switch (LCS) structure [10]. Multiline and active mechanical-breaker are two ideas to improve the technology of hybrid breakers [11, 12]. On the other hand, the fault current limiters are types of protection devices, which are lately used to improve HVDC protection capability [13]. In [14, 15] inductive fault control limiters (FCLs) are proposed to protect the grid from high raising time of fault current. A superconductive technology-based FCL is studied to improve hybrid HVDC breaker in [16, 17]. In [18], a DC reactor solid-state FCL is presented for HVDC applications that uses the superconductive technology with high capability of DC fault current limiting. ABB hybrid DC breaker [18] and Alstom hybrid breaker [19] are two commercialised HVDC breakers. For the recent HVDC grid projects, several commercialised HVDC CBs are proposed [20–22]. In [20], a mechanical breaker as the main breaker (MB) is connected in parallel with L–C commutation branch. The inductor of the topology is coupled with a low-voltage controlling circuit. A DCCB is proposed in [21] that is implemented by using the current commutation drive circuit and series modulus. In [22], a hybrid DC breaker is proposed which H-bridge modules using diodes and IGBTs are functioning as the MB and transfer branch. The capability of reclosing is an important issue that is considered in [23]. A multi-port DCCB is introduced in [24]. In this study, a hybrid bridge-type HVDC breaker [hybrid bridge breaker (HB-B)] is proposed. HB-B comprises LCS, parallel insulated gate-bipolar transistor (IGBT) MBs, power diodes, ultra-fast disconnector (UFD), and a DC reactor. The main merits of HB-B are as follows: Limiting fault current's rate of rising by a controllable DC reactor. Decreasing of the MB dissipated energy by a bypassing reactor. Fast operating time (<3 ms). Resistive fault current limiting in the MB operation. The rest of the paper is organised as follows: Section 2 presents HB-B configuration and operation. In the next section, analytical studies are given in three operation modes. In Section 4, the developed control strategy is presented. In Section 5, simulation results are reported. Experimental test results are presented in Section 6, and in Section 7 conclusions are summarised. 2 HB-B configuration and operation Fig. 1a shows the topology of the proposed breaker. In this breaker, S1 is an LCS, which in the normal operation mode conducts all current of the HVDC line. This switch is connected in series with the DC reactor. L1 is considered a 100 mH DC reactor air gap ferromagnetic reactor [24]. This reactor works as a linear inductor in all operational states. This value is chosen because of the limitation of power loss and system stability [24] and [25]. Switch S4 is a bypass switch. By turning on S4 stored energy in L1 dissipates through R3. The value of R3 is a fixed value depends on DC reactor L1 current discharging time constant. The main bridge comprises of D1, D2, S2, and S3. D1 and D2 are diodes, which conduct the DC line current in series with LCS during the normal operation. S2 and S3 are high-voltage MBs, which are connected in series with the resistors R1 and R2, respectively. They can limit fault current when current is commuted to the MB switches and damp system stored energy. Rated voltage of S1 and peak value of fault current determines a fixed value for R1 and R2. This topology is presented as a unidirectional breaker, which is simply available for modifying to a bidirectional breaker, by adding antiparallel IGBTs. As shown in Fig. 1b, in a bipolar HVDC transmission line, four breakers are placed at the sending and receiving ends of the HVDC line. The operational features of the proposed HB-B are presented in the following three states. Operational data are given in Table 1. Fig. 1Open in figure viewerPowerPoint HB-B configuration and placement (a) Proposed HB-B, (b) HB-Bs location in an HVDC line Table 1. HB-B operation states S1 S2 S3 S4 D1 D2 D3 D4 UFD normal operation (steady-state) — ON ON ON OFF ON ON OFF OFF closed normal operation (system dynamics) — ON ON ON OFF ON ON ON ON closed fault condition stage 1 — ON ON ON OFF ON ON OFF OFF closed fault condition stage 2 — OFF ON ON ON ON ON OFF OFF closed fault condition stage 3 — OFF ON ON ON ON ON OFF OFF opened fault condition stage 4 — OFF OFF OFF ON OFF OFF OFF OFF opened reclosing operation — ON ON ON OFF ON ON ON ON closed 2.1 Normal operation (steady-state) In this operation mode, the HVDC system works under steady-state conditions. In this state, HB-B conducts the DC line current. The current path is shown in Fig. 2. Accordingly, D1, UFD, L1, S1, and D2 are conducting the DC line current. L1 is the DC reactor current limiter, which is located in the middle branch of the full-bridge and its operation is controlled by the IGBT switch S4. In the steady-state operation, there is no current variation and DC reactor voltage drop is zero. Fig. 2Open in figure viewerPowerPoint Equivalent circuit of HB-B in the normal operation mode 2.2 Normal operation (dynamic mode) In this operation mode, there is no fault current, but the system is in the dynamic state. In HB-B topology, line current path is similar to the previous operation mode. However, the DC reactor decreases current's rate of rise. In addition, stored energy in the DC reactor discharges in two freewheeling circuits as shown in Fig. 3 comprised S1, D3, R1, D1 and S1, D2, R2, D4. In this operation mode, the stored energy of L1 in a dynamic state is damped. Fig. 3Open in figure viewerPowerPoint Equivalent circuit in the dynamic mode 2.3 Fault current breaking operation mode In this operation mode, a short circuit fault take place. Therefore, DC will be rapidly increased. In this mode, HB-B behaves in four consecutive stages. In the first stage, fault current's rate of rise will be limited by the DC reactor. Next, LCS interrupts current in the bridge middle branch to commutate current into the MBs S2 and S3. Moreover, in this stage, S4 turns on to discharge the stored energy of L1 into R3. In the third stage, UFD opens after a short delay to protect S1 and S4 from overvoltage. In the final stage, fault current passes through two parallel paths, which each of them conducts half of the limited fault current. In each of the MBs S2 and S3, resistances R2 and R3 are connected in series. Series resistors are able to limit fault current and dissipate the system stored energy. Fig. 4 shows current in the fault breaking state. Fig. 4Open in figure viewerPowerPoint Equivalent circuit of HB-B in the breaking mode 2.4 Reclosing operation mode After fault clearance, HB-B is ready to reclose the DC line. In this operation mode, the breaker recloses the HVDC line by turning-on S1 and closing UFD. Consequently, line current will pass through D1, D2, S1, and UFD. On the other hand, the DC reactor connected in series to the DC line limits rate of raising current (RRC). Table 1 summarises all the operation modes. 3 Analytical studies In this section, analytical studies of the HB-B is presented in the three operation modes to indicate voltage drops and breaker power losses in each state. 3.1 Normal operation (steady-state) In the normal operation mode, the line DC is in its nominal value. Line current has no variation. Voltage drop can be explained as follow: (1) (2)In (1) and (2), VD1 and VD2 are voltage drops of D1 and D2, respectively. Rd and Ld are resistance and inductance of the DC reactor. DC line current is iline and VS1 is a voltage drop of S1. The voltage drop of this state is very low because of the low impedance and steady-state line current. On the other hand, power loss depends on D1, D2, and S1 voltage drop and DC reactor resistance, which is negligible. Equation (3) expresses the normal operation power losses (3) 3.2 Normal operation (dynamic mode) During the dynamic mode, DC reactor energy charges by the line current and it limits current's rate of rise while line current rises. In this state, line current and HB-B voltage drop are as follows: (4) (5)In (4) and (5), iLine (0) is the line current value right before the dynamic state. Va and Vb are sending end and receiving end voltage, respectively. RLine is the line resistance. In addition, Req and Leq are equivalent resistance and inductance of the entire DC system. Whenever the line current falls, the DC reactor stored energy will discharge to the damping resistor. In this state, the line current expresses as follows: (6) (7) (8)In (6), id and ifw are DC reactor and freewheeling current and in (7) Rfw is the freewheel resistance as R1/2 = R2/2. In addition, power losses as a function of time are presented in (9) and (10) for charging and discharging mode. DC reactor charging mode (9)DC reactor discharging mode (10) 3.3 Breaking mode In this study, it is supposed that the short circuit fault has occurred and HB-B is studied in stages 1–4 as presented in Table 1. In stage 1, topology has no change and the only effect is limiting fault current's rate of rise with the DC reactor. This operation is described by (4) and (5) applying new Req and Leq considering the fault state. In stage 2, LCS interrupts the current of the middle branch of the bridge and the current of the MBs rapidly rise. In addition, switch S4 bypasses DC reactor with resistance R3. In this operation mode, line and DC reactor current can be expressed by (11) and (12) (11) (12)Here, RB is the resistance of the MB branches that are connected in parallel as RB = R1/2 = R2/2, where R1 = R2. In this operation mode, power loss is as follows: (13)In stage 3, UFD disconnects the LCS. In stage 4, the system stored energy discharges to R1, R2, and surge arresters. In HB-B, the transient voltage of the breaker is limited because of the following reasons: Two parallel branches for the MBs. Series resistances R1 and R2. Bypassed DC reactor. Accordingly, in stage 4, where all of the switches are turned-off, arrester voltage can be expressed as follows: (14)Here, is the resistance of the arrester, and it is a function of the MB switch voltage. 4 Control strategy In this section, the control strategy of the proposed HB-B is presented. As seen in Fig. 5, the line current, line voltage, and current's rate of rise are controlled by monitoring inputs. Line current is compared to current reference values by Comp. (2) and voltage signal is compared to voltage reference value by Comp. (2) and output of both comparators input to OR logic gate. On the other hand, the signal of current convert with analogue to digital converter and the rate of raising current is generated and compared with its reference value. The output of comp.1 input to the OR digital gate. This signal comparison can generate appropriate pulses for DC breaker UFD and solid-state switches. In this control diagram, the control command of S1 and UFD are sent at the same time after detecting the fault. In this controlling section, firstly, S1 turns-off and after a small operational delay UFD starts the opening process. Command of S4 is the invert of S1. In addition, commands of S2 and S3 are sent after a delay, depending on UFD operation (insolation recovery time). Fig. 5Open in figure viewerPowerPoint Control strategy diagram For the reclosing process, we have a fault removal block that is able to reset fault detector to change controlling logic commends of all-solid-state and UFD switches as shown in Table 1 (normal operation (system dynamics)). 5 Simulation results In this section, simulations of the proposed HB-B are carried out considering the presented diagram in Fig. 1. In the developed simulation model, line-to-ground voltage is 200 kV and line nominal current is 2 kA. The simulation scenarios are divided into three time periods. The simulation parameters are listed in Table 2. Table 2. Simulation model data Symbol Description Value Va output voltage of VSC 1 200 kV Vb output voltage of VSC 2 199 kV ILine line nominal current 2 kA RLine line resistor 0.5 Ω Lline line inductor 30 mH Rd DC reactor resistor 0.05 Ω Ld DC reactor inductor 100 mH R1 MB resistor 2 Ω R2 MB resistor 2 Ω R3 DC reactor damping resistance 200 Ω RF resistance of the fault 0.01 Ω Line current is shown in Fig. 6a while the line to ground fault is started at t 0 = 2 ms, and during t 0 till t 1 fault current is limited by the DC reactor and LCS is turned off in t 1 which line experiences the peak of the fault current. The value of the line current at t 1 is <3 kA. During t 1–t 2 line current, commutate to parallel MBs, and its value reaches 2.2 kA at t 2 because of the resistive current limiter R1 and R2. At t 2 = 4 ms the MBs (S2 and S3) are turned off to break the fault current. While the MBs are ready to break, the current of the line is close to the nominal line current. Fig. 6Open in figure viewerPowerPoint HB-B simulation results (a) DC line fault current during HB-B operation, (b) Voltage stress of the MBs, (c) Voltage stress of LCS, (d) LCS current, (e) Current of the MBs Fig. 6b illustrates the voltage of the MB switch. At t 2, by opening S2 and S3, voltage raises to 360 kV. In t 3, voltage falls to 200 kV while the line current completely breaks. Fig. 6c shows the voltage of LCS in all breaker operation modes. The peak voltage of these switches reaches 2500 V, which is a low value. Therefore, in this low voltage, the high current switch remains safe. Fig. 6d presents the current profile of LCS which its nominal value is 2 kA and its peak current after the fault occurrence increases to 2.2 kA. Here, it is clear that switch current is limited by the DC reactor until t 1 while the switch is turned off. Fig. 6e presents current of S2 as the current profile of one of the MBs. In the fault occurrence at t 0, DC reactor limits the current of the full-bridge middle branch. Therefore, MBs currents are increased until t 1. When S1 turns off, the current of the MBs increases to 1.4 kA and falls to 1.2 kA at t 2 that is much less than the line nominal value. At t 2, MBs operate to break the line current. From t 2 to t 3 MB passes the current to the surge arrester to dissipate the system stored energy. Consequently, it is shown that MBs rated currents are lower than the line current even in the fault event. This feature significantly enhances the breaker performance in comparison with already in the market hybrid breakers. The operational data of the proposed HB-B is given in Table 3. Switch current, voltage, and period of events are presented in all operation modes of the HB-B. Table 3. Operational data of HB-B Time period Measured data value (t 0–t 1), 0.7 ms peak voltage of S1 2500 V peak voltage of S2 0 V peak voltage of S3 0 V peak current of S1 2.2 A peak current of S2 0.6 A peak current of S3 0.6 A (t 1–t 2), 1.3 ms peak voltage of S1 1500 V peak voltage of S2 0 V peak voltage of S3 0 V peak current of S1 0 A peak current of S2 1.4 kA peak current of S3 1.4 kA (t 2–t 3), 1 ms peak voltage of S1 1500 V peak voltage of S2 360 kV peak voltage of S3 360 kV peak current of S1 0 A peak current of S2 0 A peak current of S3 0 A arrester peak current 1.2 kA 6 Experimental validation In this section, a scaled-down experimental prototype is developed and implemented to validate the simulation results. Data of the prototype elements are presented in Table 4. Table 4. Experimental setup parameters Symbol Description Value Vs nominal voltage of VSC 100 V ILoad load current 2 A RLine line resistance 0.5 Ω Lline line inductance 30 mH Rd DC reactor resistance 0.1 Ω Ld DC reactor inductance 100 mH C DC link capacitor 10 mf R1 MB series resistor 2 Ω R2 MB series resistor 2 Ω R3 DC reactor damping resistor 200 Ω RF resistance of the fault 0.01 Ω LCS 500 V, 10 A IGBT — MB 1000 V, 20 A IGBT — Fig. 7 depicts the developed prototype setup. In this setup, a VSC feeds a DC load through a modelled DC line and the proposed HB-B. In this examination, DC link to ground fault is formed using a mechanical switch. By detecting a fault, HB-B activates by the operational pattern presented in Table 1. Measured voltage and current signals are reported in Fig. 8. Fig. 7Open in figure viewerPowerPoint Developed experimental prototype of HB-B Fig. 8Open in figure viewerPowerPoint HB-B experimental test results (a) DC-link current, (b) HB-B voltage stress, (c) Current of LCS, (d) Current of the MB Fig. 8a presents DC link current during normal and fault conditions. In this signal, normal current magnitude is 2 A and the peak of the fault current reaches 3 A. Delay of the proposed HB-B from fault occurrence until line current zero-crossing is ∼3 ms. Fig. 8b presents the voltage stress of HB-B during the opening of DC link in the fault state. The maximum voltage of the MBs reaches 180 V, i.e. less than two times the normal voltage. Figs. 8b and c present current of LCS and MBs, respectively. It is shown that after fault, the peak current of LCS increases to 2.5 A and the peak current of the MB reaches 1.25 A. All the experimental results thoroughly confirm simulation results reported in Fig. 6. 7 Comparison study According to the presented values, a brief comparison between HB-B and the conventional hybrid DC breaker [16] is presented in Table 4. In this section, experimentally verified simulation results are compared to in market DC breaker prototype results. In this comparison, base voltage and current are assumed to be 200 and 2 kA, respectively. The rated voltage of each IGBT unit assumed to be 4.5 kV [26] (Table 5). Table 5. HVDC breakers comparison Features Hybrid breakera HB-B peak voltage of the MB 3 pu 1.8 pu peak current of the MB 2.4 pu 0.7 pu number of the MB switches 134 160 dissipated energy on the arresters 2.75 MJ 1.76 MJ operation time 5 ms 2.9 ms a Data are taken from [18]. It is evident that the proposed HB-H breaker rate of raising current, peak current, and voltage of the MB are significantly less than the hybrid breaker. This issue causes that breaker switches safety significantly increases. In addition, operation time and dissipated energy value decrease as well. Besides, Table 6 shows a comparison of used equipment in both DC breakers, which can result in cost reduction. Table 6. HVDC breakers used equipment comparison Sections Hybrid breaker* HB-B LCS one packaged IGBT, 4.5 kV, 4.8 kA 1 packaged IGBT and diode, 4.5 kV, 2.9 kA MB 134 series IGBT, 4.5 kV, 4.8 kA 160 series IGBT, 4.5 kV, 1.4 kA limiter DC reactor one reactor, 100 mH 1 reactor, 100 mH arresters metal oxide arrester, peak voltage 600 kV, 2.75 MJ Metal oxide arrester, peak voltage 360 kV, 1.76 MJ controlling switch — IGBT, 10 kV, 100 A Presented comparison in Table 6 reveals that rated current and voltage of all sections of HB-B is less than DC hybrid breaker that is evident to the cost reduction. 8 Conclusion The fast and safe operation of HVDC breaker in the event of a fault is one of the main concerns in HVDC grids. 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