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A Novel SiC MOSFET Embedding Low Barrier Diode With Enhanced Third Quadrant and Switching Performance

2020; Institute of Electrical and Electronics Engineers; Volume: 41; Issue: 10 Linguagem: Inglês

10.1109/led.2020.3017650

1558-0563

Xiaochuan Deng, Xiaojie Xu, Xuan Li, Xu Li, Yi Wen, Wanjun Chen,

Advancements in Semiconductor Devices and Circuit Design

A novel planar gate SiC MOSFET embedding low barrier diode (LBD-MOSFET) with improved third quadrant and switching performance is proposed and characterized in this letter. The LBD-MOSFET not only exhibits about 3 times lower diode turn on voltage than the body diode, but also successfully eliminates bipolar degradation phenomena. A low potential barrier for electrons transporting from JFET region to N + source region is formed in LBD-MOSFET owing to the existence of the depletion charge in LBD base region. Meanwhile, the gate-to-drain charge (Q gd ) and gate-to-drain capacitance (C gd ) of LBD-MOSFET are significantly reduced by about 21× and 15× in comparison with the conventional MOSFET (C-MOSFET), due to the reduction of the overlapping area of the gate and drift region. Therefore, the obtained high frequency figures of merit (HF-FOM1 = R on,sp × Q gd and HF-FOM2 = R on,sp × C gd ) for the LBD-MOSFET are improved by about 13 times and 9 times compared with C-MOSFET. Furthermore, a compact potential barrier analytical model based on Poisson's Law is developed to understand the origin of low potential barrier diode in SiC LBD-MOSFET. The overall enhanced performances suggest SiC LBD-MOSFET is an excellent choice for high frequency power electronic applications.