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Asymmetric cascade multilevel inverter with self‐balanced switched‐capacitor unit and single source

2020; Institution of Engineering and Technology; Volume: 13; Issue: 15 Linguagem: Inglês

10.1049/iet-pel.2019.1098

1755-4543

Yuanmao Ye, Mingliang Lin, Xiaolin Wang,

Silicon Carbide Semiconductor Technologies

IET Power ElectronicsVolume 13, Issue 15 p. 3254-3262 Research ArticleFree Access Asymmetric cascade multilevel inverter with self-balanced switched-capacitor unit and single source Yuanmao Ye, Yuanmao Ye School of Automation, Guangdong University of Technology, Guangzhou, People's Republic of ChinaSearch for more papers by this authorMingliang Lin, Mingliang Lin School of Automation, Guangdong University of Technology, Guangzhou, People's Republic of ChinaSearch for more papers by this authorXiaolin Wang, Corresponding Author Xiaolin Wang xiaolinwang@gdut.edu.cn School of Automation, Guangdong University of Technology, Guangzhou, People's Republic of ChinaSearch for more papers by this author Yuanmao Ye, Yuanmao Ye School of Automation, Guangdong University of Technology, Guangzhou, People's Republic of ChinaSearch for more papers by this authorMingliang Lin, Mingliang Lin School of Automation, Guangdong University of Technology, Guangzhou, People's Republic of ChinaSearch for more papers by this authorXiaolin Wang, Corresponding Author Xiaolin Wang xiaolinwang@gdut.edu.cn School of Automation, Guangdong University of Technology, Guangzhou, People's Republic of ChinaSearch for more papers by this author First published: 21 September 2020 https://doi.org/10.1049/iet-pel.2019.1098Citations: 4AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract The technique of single-source cascaded H-bridge multilevel inverter (MLI) has been reported in previous works. In this study, a self-balanced series/parallel switched-capacitor (SC) is introduced to further develop this type of MLIs to generate more output levels. Each cascaded H-bridge is fed by an SC unit. All components in each SC unit withstand the same voltage stress, but different SC units address different voltages. With this asymmetric feature, different H-bridges are responsible for providing levels with different voltage intervals so that the cascaded MLI can generate numerous levels with a single dc source and fewer components. Compared with the conventional asymmetrical cascaded MLIs, just a single dc source is required, capacitors' voltages are balanced automatically, high boosting ability and more output levels are achieved with SC technique in the proposed MLIs. To synthesise the output voltage as close as possible to sinusoidal shape but with less switching loss, comparative analysis of nearest level control and equal area criterion is provided to modulate the proposed MLI with 13-level output. Experimental results demonstrate that the proposed MLI has high efficiency and low harmonics. 1 Introduction To obtain a nearly sinusoidal ac output voltage waveform is becoming more and more important for the growing demand for high-performance power supplies in industrial applications. Multilevel inverter (MLI) technique has therefore been receiving much attention as it has several attractive advantages such as reduced dv/ dt stresses, near-sinusoidal staircase output voltage waveforms and operating with lower switching frequency etc. [1, 2]. Conventional MLIs can be divided into three categories: neutral-point-clamped (NPC), flying capacitor (FC) and cascaded H-bridge (CHB) [3, 4]. Both NPC and FC MLIs suffer from the problem of unbalanced capacitor voltages [5]. Moreover, a large number of clamped components are employed in these two types of MLIs, particularly when the number of output levels is large [6]. For CHB, it has the simplest structure and there is no voltage unbalance problem, but a large number of isolated dc voltage sources are required [7]. In recent years, modular multilevel converter (MMC) technology has become a research hotspot [8]. Switched-capacitor (SC) technique has also been successfully used to develop a new type of MLIs. Most SC-based MLIs have the advantage of self-balanced capacitor's voltages. For instance, the works of [9, 10] take the conventional series/parallel SC circuit and its simplified version to develop MLIs. Similarly, a modified series/parallel SC-based MLI is developed for higher boosting ability in [11]. A step-down SC circuit and an SC-based triple circuit are taken to develop MLIs in [12, 13], respectively. In these MLIs, as all capacitors are connected in series and parallel alternately, their voltages can be equalised automatically without the need for auxiliary circuits and complicated control algorithms. In contrast, self-balanced capacitors' voltages in the works [14-17] are implemented by charging capacitors multiple times during one cycle of the output voltage. Moreover, capacitors in SC circuits operate in charging and discharging modes alternately; their voltages can, therefore, maintain constant dynamically but with some small ripples [18]. As a result, precharged capacitors in SC-based MLIs are taken as dc voltage sources and this feature has been successfully used to optimise the structure of CHB. For instance, a cascaded 7-level inverter with a single dc source and three H-bridges is developed based on the SC technique in [19, 20]. As shown in Fig. 1a, only one H-bridge in this structure is fed by the dc source directly and the other two are fed by precharged capacitors. Between any two adjacent H-bridges, there is a bidirectional switch used to provide a charging path for capacitors. The same method is also used in [21] to cascade the T-type inverting unit with H-bridges for both symmetric and asymmetric structures of single-source MLIs. In work [22], all cascaded H-bridges are fed by precharged capacitors. As shown in Fig. 1b, only one dc source is used to replenish energy to these capacitors through a switched-diode network. Fig. 1Open in figure viewerPowerPoint Cascaded CHB with single dc source (a) Topology presented in [19, 20], (b) Topology presented in [22] In addition to using SC technology to simplify the circuit structure of MLIs, the asymmetrical cascaded structure is also a very important technique to get more output levels with less components [23]. However, multiple dc sources with different voltages are required in this type of topologies [24, 25]. Otherwise, advanced control algorithms with sensor networks are required to control capacitors' voltages in auxiliary inverters, as described in [26-30]. In this paper, these techniques of Fig. 1 are further developed by inserting an SC cell in each H-bridge to increase the number of output voltage levels. Each SC cell consists of multiple semiconductor switches and several capacitors operated in series and parallel manners alternately. Only one dc source is required to charge all capacitors of the proposed MLI. Especially, with two cascaded H-bridges, the two inserted SC units may have the same structure, but one of them is used as a high-voltage unit and the other is used as a low-voltage unit. All capacitors in the high-voltage unit are charged in parallel and they can generate multiple levels with large voltage intervals, while all capacitors of the low-voltage unit are charged in series and they can provide several levels with a small voltage interval. Compared with the existing SC-based H-bridge MLIs shown in Fig. 1, much more output voltage levels can be generated from a single dc source with the proposed MLI. Compared with the asymmetrical cascaded MLIs introduced in [23-30], capacitors' voltages of the proposed MLIs have balanced automatically and high boosting ability is achieved with SC technique. Other sections of this paper are organised as follows: Section 2 describes the circuit configuration and operation principle of the proposed MLI. Modulation strategies for the proposed MLI with 13-level are introduced and compared in Section 3. In Section 4, voltage ripples of capacitors and capacitance determination are described. Then, power loss is analysed in Section 5. Section 6 gives experimental results of the proposed MLI with 13-level. Finally, the paper is concluded in Section 7. 2 Proposed MLI 2.1 Cascaded H-bridge with asymmetric SC units Fig. 2 shows the basic circuit configuration of the cascaded MLI with two H-bridges and two series/parallel SC units. Each SC unit is made up of two capacitors and three semiconductor switches. All components employed in each SC unit withstand the same voltage stress and this is very suitable for modular design. Voltages of the two SC units are distributed in an asymmetric way, i.e. the first unit withstands the voltage of E while the second one withstands 2E. The switches Ti 1 and Ti 2 are turned ON/OFF simultaneously while Ti 3 operates in complementary with them, here i = 1 or/and 2. As a result, the first H-bridge is capable of generating the levels 0, ±E and ±2E while the second one provides 0, ±2E and ±4E. Finally, the cascaded MLI can generate 13 different voltage levels that are 0, ±E, ±2E, ±3E, ±4E, ±5E and ±6E. Fig. 2Open in figure viewerPowerPoint Cascaded MLI with asymmetric series/parallel SC units 2.2 Charging and balancing of capacitors In each SC unit, the two capacitors operate in series and parallel manners alternately so that their voltages can be balanced automatically. However, to ensure that the two SC units' voltages are distributed in the asymmetric relationship aforementioned, i.e., one is E and another is 2E, an additional balancing path provided by a bidirectional switch is added, as shown in Fig. 3a. With this balancing path, energy can flow in both directions between the two SC units so that their voltages' ratio can maintain at 1:2. Fig. 3Open in figure viewerPowerPoint Asymmetric cascaded MLI with single dc source (a) Additional balancing path for capacitors, (b) Circuit configuration 1, (c) Circuit configuration 2 When the MLI is used to power loads, capacitors' voltages will drop gradually as energy flows out of them. Hence, dc power sources are required to charge capacitors so that their voltages can be constant. Usually, multiple dc sources with different voltages are employed in asymmetric cascaded MLI. For instance, each cascaded SC-based H-bridge is fed by a dc source in work [31]. In contrast, only one dc source is required in the proposed MLI as the existence of the capacitors' voltage balancing path illustrated in Fig. 3a. Specifically, a dc source with voltage E can be connected in parallel with one capacitor of the first SC unit to charge all capacitors, as illustrated in Fig. 2b. In this circuit configuration, the capacitor C 12 is charged by the dc source directly through the switches T 11 and T 12 while C 21 and C 22 are charged by the dc source and C 11 together through the balancing path illustrated in Fig. 3a. In addition, the dc source can also be connected in parallel with one capacitor of the second SC unit as depicted in Fig. 3c, but its voltage should be adjusted to 2E. In this case, C 22 is charged by the dc source directly through the switches T 21 and T 22, while C 11 and C 12 are also charged by the dc source directly through the balancing path given in Fig. 3a. 2.3 Operation principle In this section, the circuit configuration of Fig. 3c is taken as an example to describe the operation principle of the proposed MLIs. Table 1 illustrates the MLI's switching scheme corresponding to 13 different output levels, wherein 1 and 0 values are indicative of ON and OFF states for the related switches, respectively, and the symbols '▴', '▾' and '⁃' are indicative of charging, discharging and idle modes for the related capacitors, respectively. Table 1. Switches and capacitors' states for the MLI of Fig. 3c Voltage levels Switching states Capacitors S 11 –S 14 S 21 –S 24 T 11 –T 13 T 21 –T 23 S ch C 11 C 12 C 22 +6E 1001 1001 001 001 0 ▾ ▾ ▾ +5E 1001 1001 110 001 0 ▾ ▾ ▾ +4E 1010 1001 110 001 0 ⁃ ⁃ ▾ +3E 1001 1001 110 110 0 ▾ ▾ ▴ +2E 1010 1001 001 110 1 ▴ ▴ ▴ +E 1001 1010 110 110 0 ▾ ▾ ▴ 0 1010 1010 001 110 1 ▴ ▴ ▴ −E 0110 1010 110 110 0 ▾ ▾ ▴ −2E 0110 1010 001 110 1 ▴ ▴ ▴ −3E 0110 0110 110 110 0 ▾ ▾ ▴ −4E 0101 0110 110 001 0 ⁃ ⁃ ▾ −5E 0110 0110 110 001 0 ▾ ▾ ▾ −6E 0110 0110 001 001 0 ▾ ▾ ▾ According to the description of Table 1, the bidirectional switch S ch is turned ON to provide a charging path for C 11 and C 22 when the output level is 0 and ±2E. Figs. 4a –c give state circuits of the three levels. During one cycle of the output voltage, the capacitors C 11 and C 12 can be charged six times for staircase output. Their voltages can, therefore, maintain at E but with some ripples, which will be analysed later. Fig. 4Open in figure viewerPowerPoint Typical state circuits for the 13-level inverter of Fig. 3 c (a) u O = 0, (b) u O = + 2E, (c) u O = −2E Considering the parasitic resistance of components, the charging loops for capacitors are redrawn in Fig. 5a. In this case, both capacitor voltage and charging current will be affected by the parasitic resistance. Referring to the work [32], there are three capacitor charging modes corresponding to different values of the parasitic resistance. When the total parasitic resistance of the charging loop is so small that the capacitor can be fully charged, variations of the capacitor voltage and charging current are shown in Fig. 5b. With a larger parasitic resistance, the charging will be partial, as depicted in Fig. 5c. When the parasitic resistance is very large, there will be no effective charging and the current will be practically constant, as shown in Fig. 5d. Anyway, the maximum charging current occurred at the switch's ON moment is determined by the total parasitic resistance and the difference between the charging voltage and the initial capacitor voltage. Too small parasitic resistance ensures that the capacitor can be fully charged, but it will cause a huge charging current spike, and vice versa. Hence, partial charging mode is more suitable for MLIs. Fig. 5Open in figure viewerPowerPoint The influence of parasitic resistance on charging current of capacitors (a) Charging loops of capacitors with parasitic resistance, (b) Variations of charging current and capacitor voltage with a very small parasitic resistance, (c) Variations of charging current and capacitor voltage with a larger parasitic resistance, (d) Variations of charging current and capacitor voltage with a very large parasitic resistance 2.4 Extension structures of the proposed MLI With the same design philosophy aforementioned, the cascaded MLI is extended to include the number of n H-bridges, as illustrated in Fig. 6a. The voltages of all SC units are distributed in 1:2:, …, :2n. Between any two adjacent H-bridges, a bidirectional switch is used to provide a charging path for capacitors. In this structure, energy can only flow between adjacent H-bridges and charging loss of capacitors will increase significantly when the number of cascaded H-bridges increases. Another extension structure is shown in Fig. 6b, of which SC units are expanded to the conventional series/parallel SC circuit [9]. There are n capacitors with voltage E in the first H-bridge while m capacitors with a voltage nE in the second H-bridge. For both structures of Figs. 6a and b, only one dc source is required to charge capacitors and it can be connected in parallel with any one capacitor. Especially, when a dc source with a voltage nE is connected in parallel with one capacitor of the second H-bridge in Fig. 6b, all capacitors of both SC units can be charged by the dc source directly and the MLI can be seen as a single-stage power conversion system. Fig. 6Open in figure viewerPowerPoint Extension structures of the proposed MLI (a) With more cascaded H-bridges, (b) With more series/parallel capacitors, (c) Replace the bidirectional switch with switched-diode network Referring to the work [22], the bidirectional switch S ch used in Fig. 6b can be replaced by a switched-diode network to provide a charging path for capacitors, as illustrated in Fig. 6c. The result is that one dc source with voltage nE is employed to charge capacitors of both SC units and the charging paths are depicted with coloured bold lines. It can be seen that all capacitors in both SC units are also charged by the dc source directly and the MLI is, therefore, a single-stage power conversion system. 3 Modulation of the proposed MLI To synthesise the output voltage as close as possible to sinusoidal waveform, there are many modulation strategies that can be used to the proposed MLI. For instance, with multicarrier PWM methods, the proposed MLI is capable of providing a higher quality of output voltage, but all switches operate in high switching frequency resulting in high switching loss. To avoid this problem, fundamental frequency modulation methods are one reasonable solution to generate a staircase output voltage. Among different fundamental frequency modulation methods, selective harmonic elimination (SHE) method has the best performance, but the switching angles have to be computed offline as they are the solution of a set of non-linear transcendental equations. In contrast, nearest level control (NLC) and equal area criterion (EAC) are simpler methods to calculate the switching angles. The two methods are, therefore analysed as follows for the proposed MLI. 3.1 Nearest level control The NLC is also known as the round method. As illustrated in Fig. 7a, gating signals of the proposed 13-level inverter can be directly determined by a given reference voltage u ref with the switching logic given in Table 1. The nearest voltage level N LV is calculated by (1) where A S is the amplitude of the sinusoidal reference voltage u ref. Fig. 7Open in figure viewerPowerPoint NLC modulation for the proposed 13-level inverter (a) Control diagram, (b) Waveform synthesis Fig. 7b shows the waveform synthesis of the proposed 13-level inverter with NLC modulation. The six switching angles θ 1 –θ 6 are determined by (2) where i = 1, 2, 3, 4, 5 and 6. 3.2 Equal area criterion Fig. 8 shows the EAC modulation for the proposed 13-level inverter. The basic ideal is illustrated in the square area of Fig. 8, i.e. SiA = SiB, here SiB is the area difference between the sinusoidal modulation waveform and the staircase waveform during the interval from βi− 1 to θi, SiA is the area difference between the staircase waveform and the sinusoidal modulation waveform during the interval from θi to βi. By the nature of the EAC, the fundamental of the staircase waveform would resemble the sinusoidal modulation waveform. Since βi− 1 and βi are two angles when the modulation signal u ref is equal to (i −1) × E and i × E, respectively, the switching angle θi can be found by solving (3) where again i ranges from 1 to 6. The left side of (3) is the area SiB and the right side is the area SiA. Solving (3), the switching angle θi is expressed as (4) Substituting βi = arcsin(iE/A S) and β 0 = 0 and β 6 = π /2 into (4), the six switching angles θ 1 –θ 6 are calculated. Fig. 8Open in figure viewerPowerPoint EAC modulation for the proposed 13-level inverter 3.3 Comparison of NLC and EAC modulations To get a complete 13-level output voltage, the amplitude A S of the reference voltage should be greater than 5.5E for NLC modulation, and be between 5E and 6E for EAC modulation, respectively. Fig. 9a shows the switching angles θ 1 –θ 6 calculated by the NLC formula (2) and EAC formula (4), respectively. It indicates that there are similar results for the two modulation methods when the amplitude of the reference voltage ranges from 5.5E to 6E. However, considering the computation of the switching angles θ 1 –θ 6 will be a burden for closed-loop control, NLC is superior to EAC as it requires lower computing costs. Fig. 9Open in figure viewerPowerPoint Switching angles and modulation index versus amplitude of the voltage reference uref (a) Switching angles, (b) Modulation index, (c) THD The Fourier transform and fundamental content of the staircase output voltage for the proposed 13-level inverter are expressed as (5) (6) The modulation index is defined as M = V 1 /6E and V 1 is the magnitude of the fundamental content of the output voltage given in (6). Fig. 9b shows the modulation index of the proposed 13-level inverter with NLC and EAC modulations. It can be seen that a higher modulation index can be achieved by NLC modulation as the amplitude of the voltage reference could be above 6E. Two total harmonic distortions (THDs) of the 13-level staircase output voltage are calculated by using the following equation: (7) Fig. 9c shows the THD of the 13-level inverter with NLC and EAC modulations. It indicates that the THD is always smaller than 8% regardless of NLC or EAC modulation. Overall, the NLC has slightly better performance and simpler calculation of switching angles than the EAC modulation. To get a higher quality of output voltage, the switching angles calculated by the NLC or the EAC could be further used as the initial values of Newton–Raphson iteration for SHE modulation. 4 Capacitance determination For the 13-level inverter of Fig. 3c, the capacitor C 22 is connected in series with the dc source to power loads during the output levels of ±4E, ±5E and ±6E. Its voltage ripple can, therefore, be calculated by (8) where i O (t) is the output current of the proposed 13-level inverter and ω is the angular frequency of the output voltage. For the capacitors C 11 and C 12, they are connected in parallel to discharge to loads during the output level of ±E and then be charged by the voltage source during the output level of ±2E. After that, they are connected in parallel to discharge during the levels of ±3E, ±5E and are connected in series to discharge during the level of ±6E. Assuming both capacitors are fully charged to the voltage of E during the level of ±2E, their voltage ripples can be calculated by (9) With a pure resistive load R, the voltage ripples can be further simplified to (10) (11) The capacitance of C 22 and C 11 /C 12 can, therefore, be determined according to their voltage ripples. It is assumed that the ratio of voltage ripple to the capacitor's maximum voltage for all capacitors is set as x % and the maximum voltages for C 22 and C 11 /C 12 are 2E and E, respectively. The capacitance can be determined by (12) (13) where f is the frequency of the output voltage, the switching angles θ 3 –θ 6 are calculated by (2) or (4). 5 Power losses analysis The total power losses, including switching loss of transistors, charging loss of capacitors as well as conduction loss caused by load current of the proposed 13-level inverter are analysed as follows. 5.1 Switching losses As analysed in [33], during one switching cycle, switching energy loss of one transistor can be simplified as (14) where C oss is the parasitic capacitance of the transistor and V DS is the switch's voltage stress. The second and third lines of Table 2 give voltage stresses V S and switching frequencies f S of all transistors employed in the proposed MLIs of Fig. 3c. Table 2. Switching losses of the 13-level inverter of Fig. 3c S S 11, S 12 S 13, S 14 S 21 –S 24 T 11 –T 13 T 21 –T 23 S ch V S 2E 2E 4E E 2E 4E f S f 7f f 8f 2f 6f P SW 8C o1 E 2 f 56C o1 E 2 f 64C o2 E 2 f 24C o3 E 2 f 24C o1 E 2 f 96C o2 E 2 f P SW_All (88C o1 + 160C o2 + 24C o3)E 2 f Then individual switching loss P SW and the total switching loss P SW_ALL are calculated as given in the fourth and fifth lines, respectively, wherein C o1, C o2 and C o3 represent the parasitic capacitances of the transistors of which voltage stresses are 2E, 4E and E, respectively. 5.2 Charging losses of capacitors During the levels of 0, ±E, 2E and ±3E, the capacitor C 22 is always connected in parallel with the dc source E and it is charged. When the total parasitic resistance of the charging loop is so small that the capacitor can be fully charged, energy loss generated in one charging process is given by (15) where ΔVC 22 is the capacitor's voltage ripple as given in (8). For one cycle of the output voltage, C 22 is charged two times. When the load is a pure resistor R, the charging loss of C 22 is given by (16) Similarly, the capacitors C 11 and C 12 are charged by the dc source for the levels of 0 and ±2E. Referring Figs. 7b or 8, there are the same voltage ripple for the charging period from −θ 1 to θ 1 and the period from θ 2 to θ 3. Energy loss of both capacitors C 11 and C 12 during the two periods is given as (17) For a pure resistive load R, (18) can be simplified to (18) For the charging period from π −θ 3 to π −θ 2, the voltage ripple for the capacitors C 11 /C 12 is given in (9). For a pure resistive load R, the energy loss of both capacitors during this period is given by (19) Charging loss of the two capacitors C 11 and C 12 is therefore given as (20) The total charging loss of capacitors is the sum of (16) and (20). 5.3 Conduction losses caused by the load current For any level of the output voltage, the load current always flows through the two full bridges, S 11 –S 14 and S 21 –S 24. Conduction loss of the two full bridges is therefore given as (21) where rS 1 and rS 2 are on-resistance of one transistor in the bridges S 11 –S 14 and S 21 –S 24, respectively, P O is the output power of the MLI. For the levels of ±E, ±3E and ±5E, the load current evenly flows through the two transistors T 11 and T 12. Moreover, for the level of ±6E, the load current flows through both transistors T 11 and T 12. Hence, conduction loss of the two transistors is given as (22) where rT 1 is the on-resistance of the transistors T 11 and T 12. In the high voltage unit, the transistor T 22 provides a path for the load current for the levels of ±2E and ±3E. For the levels of ±4E, ±5E and ±6E, the transistor T 23 provides the current path. Conduction loss of the two transistors T 22 and T 23 is therefore given as (23) where rT 2 is the on-resistance of the transistors T 22 and T 23. The total conduction loss caused by the load current is the sum of (21)–(23). 6 Experimental results To verify the feasibility of the proposed MLI, a 13-level inverter was a built-in laboratory. The circuit configuration of the prototype is implemented by referring to Fig. 3c. Its specification and components are given in Table 3. Fig. 10 shows the experimental bench, wherein the DSP controller is used to generate gate signals of the 13-level inverter. Fig. 10Open in figure viewerPowerPoint Experimental benches for the proposed MLI Table 3. Specification and components of the 13-level inverter Input voltage, 2E 80VDC frequency of output voltage f S 50 Hz C 11, C 12 2200 μF C 21, C 22 2 × 1000 μF S 11∼4, T 11∼3, T 21∼3 (N -channel MOSFET) IRFI4410ZPBF S 21∼4 (N -channel MOSFET) IRFB4332PBF S ch IRF640 loads 50 Ω/100 Ω (−53 mH) As NLC has better performance and simpler calculation of switching angles than EAC modulation, it was selected to modulate the 13-level prototype and was implemented in TMS320F28335. There are seven gate signals of the inverter given in Fig. 11, while other eight gate signals can be derived from them by utilising complementary relationships of switches. Fig. 11Open in figure viewerPowerPoint Gate signals of switches employed in the 13-level inverter When the amplitude A S of the reference voltage u ref is set to 6E, the switching angles θ 1 –θ 6 calculated by (2) are 4.78°, 14.48°, 24.63°, 35.69°, 48.59° and 66.44°, respectively. Fig. 12a shows the experimental waveforms of the output voltage and capacitors' voltages when the load is a pure resistive load 50 Ω. It shows that capacitors' voltages are balanced and with some ripples. The measured rms value of the output voltage is 156.7 V. It is obviously lower than the theoretical value 169 V and the difference is caused by capacitor voltage ripples. As shown in Fig. 12b, the voltage ripples of capacitors decrease significantly when the load increases to 100 Ω. This result is consistent with the theoretical analysis given in (10) and (11). The rms value of the output voltage also increases to 162 V and it is closer to the theoretical value 169 V. In order to suppress the effect of capacitor voltage ripples on the output voltage, one mean is to use larger capacitors and another mean is to increase the frequency of the output voltage as analysed in [10]. Fig. 12Open in figure viewerPowerPoint Experimental waveforms for pure resistive loads (a) R = 50 Ω, (b) R = 100 Ω Fig. 13 shows the current of the bidirectional switch S ch and the variation of the capacitor voltage VC 11. The switch current iS ch is also the charging current of the capacitors C 11 and C 12. It shows there are six times to charge the two capacitors during one cycle of the output voltage, i.e. u O = 0 and u O = ±2E. The bottom of this figure indicates that the capacitors of this MLI operate in a partial charging mode and the charging current spike at switching instants is successfully limited by the on-resistance of the bidirectional switch. This is very important for EMI reduction. In [19], the charging current spike is also limited by parasitic resistance and the work [20] does not cover this issue. In [22], the charging current spike is limited by inserting a small inductor in series with the charging switch. Overall, the EMI problem caused by the charging current of capacitors in this type of MLIs can be effectively suppressed by utilising parasitic resistance of components. Fig. 13Open in figure viewerPowerPoint Charging current and variation of capacitor voltage when R = 50 Ω When the inverter is used to power an inductive load 50 Ω–53 mH, experimental results are shown in Fig. 14. The output voltage is still staircase shape but the load current changes to sinusoidal waveform as illustrated in Fig. 14a. Their rms values are 159.2 V and 2.99 A, respectively, and there is a phase difference of about 20° between them. Compared with the results shown in Fig. 12a, capacitors' voltage ripples are significantly reduced. One reason is that the impedance increases from 50 to 52.6 Ω. Another reason is that the capacitors are replenished by absorbing the reactive power of the inductive load. Hence, the smaller capacitance can be used for inductive load. However, lower efficiency is usually caused by inductive loads. Fig. 14b gives FFT results of the output voltage and current for the experimental result. It indicates that there are few low-order harmonics for the output voltage and high-order harmonics of the output current have been effectively suppressed by the R-L load. Fig. 14Open in figure viewerPowerPoint Experimental results for an inductive load 50 Ω–53 mH (a) Waveforms, (b) FFT results of the output voltage and current Fig. 15 shows the experimental waveforms with the dynamic load. It indicates that the output voltage remains stable when the load is quickly switched between 50 Ω–53 mH and 100 Ω–53 mH. Fig. 15Open in figure viewerPowerPoint Experimental waveforms when the load changes between 50 Ω–53 mH and 100 Ω–53 mH Finally, when the pure resistive load was changed from 50 to 300, in 50 Ω increments, the efficiency of the 13-level prototype was measured as depicted in Fig. 16. It indicates that the inverter maintains high efficiency when output power varies from 97 to 490 W and the maximum value is up to 97.1%. Fig. 16Open in figure viewerPowerPoint Measured efficiency of the 13-level prototype 7 Conclusions Combining single source cascaded H-bridge and asymmetric SC techniques, a new MLI is proposed to generate more output levels. In the proposed MLI, each cascaded H-bridge is fed by a series/parallel SC unit and different H-bridges are responsible for providing multiple levels with different voltage intervals. All capacitors are charged by a single dc source through either bidirectional switches or a switched-diode network. With fundamental frequency modulation, the simplest version of the proposed MLI can provide 13 different levels with staircase shape and more levels can be generated by the extended structures. Compared with the works [18, 19, 21], fewer components are required, but more levels can be generated by the proposed MLI. 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