Interleaved high step‐up ZVS DC–DC converter with coupled inductor and built‐in transformer for renewable energy systems applications
2020; Institution of Engineering and Technology; Volume: 13; Issue: 16 Linguagem: Inglês
10.1049/iet-pel.2020.0162
ISSN1755-4543
AutoresTohid Nouri, Mahdi Shaneh, Alireza Ghorbani,
Tópico(s)Multilevel Inverters and Converters
ResumoIET Power ElectronicsVolume 13, Issue 16 p. 3537-3548 Research ArticleFree Access Interleaved high step-up ZVS DC–DC converter with coupled inductor and built-in transformer for renewable energy systems applications Tohid Nouri, Corresponding Author Tohid Nouri Thdnouri@gmail.com orcid.org/0000-0003-1899-9097 Department of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, IranSearch for more papers by this authorMahdi Shaneh, Mahdi Shaneh Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, IranSearch for more papers by this authorAlireza Ghorbani, Alireza Ghorbani Department of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, IranSearch for more papers by this author Tohid Nouri, Corresponding Author Tohid Nouri Thdnouri@gmail.com orcid.org/0000-0003-1899-9097 Department of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, IranSearch for more papers by this authorMahdi Shaneh, Mahdi Shaneh Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, IranSearch for more papers by this authorAlireza Ghorbani, Alireza Ghorbani Department of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, IranSearch for more papers by this author First published: 01 December 2020 https://doi.org/10.1049/iet-pel.2020.0162Citations: 3AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract A zero voltage switching (ZVS) interleaved high step-up converter with coupled inductor and built-in transformer voltage multiplier cell is introduced in this study. A more flexible design is provided by increasing the voltage conversion ratio by utilising the turns ratios of the coupled inductor and built-in transformer. The ZVS operation of the metal-oxide-semiconductor field-effect transistors (MOSFETs) and absorption of the leakage current are realised through active clamp circuits. Furthermore, the voltage stress across the switching devices is minimised that give rises to implementation of low voltage rated MOSFETs and consequently low conduction losses. Meanwhile, the diode reverse current problem is alleviated by the leakage inductance of the coupled inductor and built-in transformer. All of the abovementioned advantages make the proposed converter as a high efficiency candidate for high current and high step-up applications. Finally, a 600 W, 48–700 V voltage conversion with the conversion efficiency of 97% is fabricated to probe the merits of the proposed converter. 1 Introduction Photovoltaic (PV) and fuel cell (FC) are known as green energy sources to feed a part of the required demanded power of the local loads and/or grids. However, high step-up DC–DC converters are necessary to match their low output voltage to the required voltage level of the loads. Theoretically, conventional boost converter appears as a suitable candidate for this purpose. However, for obtaining high voltage conversion ratio, the duty cycle should be set around unity. Working at extreme duty cycle along with high voltage and current stress increases the conduction losses and reduces the conversion efficiency and the controllability. Altogether, the application of this converter is limited when high voltage and high current is demanded [1]. Cascade boost converters realise high quadratic voltage gain which avoids high duty cycles. Although, the voltage stresses across the switching devices are relatively low; however, the metal-oxide-semiconductor field-effect transistor (MOSFET) and diode at the second stage suffer from high output voltage. The MOSFET in the first stage can be operated at high switching frequency and the one in the second stage should be switched at low frequency to avid high switching losses. Moreover, due to multi-stage power processing, the efficiency is decreased, considerably [1]. Many techniques such as switched capacitors (SCs) and/or switched inductors, voltage multiplier cells (VMCs) [2-4], voltage lift with VMC [5-7], coupled inductor with VMC [8-16] and Z-source converters [17, 18], have been proposed to increase the voltage conversion ratio of the conventional boost converter while the switches are operated at moderate duty cycles. Implementation of low voltage rated MOSFETs with low ON-state resistance is facilitated in these topologies because of reduced voltage stress across the switching devices. Also, in the converter with coupled inductors, the leakage energy is absorbed by passive clamps avoiding large spikes on MOSFETs. However, the ripple of the input current is high in these converters which seriously damages the PV and FC. Interleaving technique is a promising solution in high power applications to reduce the component size, increase the power level while maintain the efficiency, minimise the input current ripple and realise the thermal distribution [18-30]. Interleaved converters with winding cross-coupled inductor technique have been introduced in [19-21] that achieve auto-current sharing performance. Built-in transformer is an interesting alternative for voltage gain step-up due to balanced flux that avoids saturation phenomenon even with a low size of the magnetic core [22, 23]. In the converters of [24, 25], the secondary of the coupled inductors is connected in series with each other to make a voltage doubler with forward/flyback characteristic which is connected in a stacked manner at the output. This technique along with the SC scheme participates to voltage gain enhancement of the introduced converter, as well. A more flexible voltage gain and lower voltage stress across the MOSFETs are achieved with the boost/forward/flyback converter in [26] by integrating three-winding coupled inductors and SC module. Unfortunately, one of the windings of the coupled inductors does not play any role for voltage gain extension and the performance is limited. In order to further increase the voltage gain, the SC VMCs in [27] share the series-connected secondary windings of the coupled inductors in the middle point of the stacked output capacitors. Although the ultra large gain is obtained, however, problems such as PV panel leakage current and safety arises in this configuration due to the lost common ground between the load and the source. For the purpose of adding an extra degree of freedom in design purposes, the proposed converters in [28-30] utilise the built-in transformer and coupled inductor techniques to increase step-up ratio, simultaneously. Although the leakage inductance can provide natural zero current switching (ZCS) in the converters of [28-30], however, it does not effectively reduce the switching losses and as a result, the switching frequency cannot be pushed to high levels for decreasing of the converter volume. Active clamp technique is utilised for zero voltage switching (ZVS) performance in [31-37]. All active switches achieve ZVS operation and both of the switching losses and the imposed voltage on the MOSFETs are significantly decreased. Motivated by the aforementioned literature review, an interleaved DC–DC converter with the following advantages is proposed in this paper: (i) High voltage conversion ratio is obtained. (ii) The imposed voltage on the power switches is minimised and all of the power MOSFETs operates under ZVS performance during whole switching cycle. (iii) A more flexible design is realised to design the converter comparing to the solutions with only coupled inductor or only built-in transformer. (iv) The diodes current falling rate is adjusted by the leakage inductances of the magnetic devices. 2 Proposed converter and operational principle Fig. 1 shows the structure of the proposed converter. The passive clamp circuits are removed and active clamp structure is added in the proposed converter. Also, the anodes of the regenerative diodes are shifted to be connected to the drain of the main MOSFET and their cathodes are connected to the multiplier capacitors in the other phase to improve current sharing performance. Lm 1 and Lm 2 are the magnetising inductances; Lk 1 and Lk 2 symbolise the leakage inductances of the coupled inductors that are referred to the primary, Lkb denotes the leakage inductance of the built-in transformer referred to the primary; S 1 and S 2 symbolise the main switches; SC 1 and SC 2 symbolise the clamp power MOSFETs; Cc 1 and Cc 2 are the clamp capacitors, Co 1, Co 2 and Co 3 denote the output capacitors, and Cm 1 and Cm 2 symbolise the multiplier capacitors; Dr 1 and Dr 2 are the regenerative diodes, Db 1 and Db 2 denote the output diodes for boost operation with SCs, Df 1 and Df 2 symbolise the output diodes for forward-flyback operation. Symbols ‘ ’ and ‘∗’ notations are used to present the coupling references of the coupled inductors. The number of the windings for each of the coupled inductors meet the with the turns ratio of n = ns /np. Symbol ‘Δ’ is utilised as the coupling reference of the built-in transformer. The number of the secondary and tertiary windings of the built-in transformer are the same with the turns ratio of N = Ns /Np. The steady-state waveforms of the proposed converter are shown in Fig. 2. Sixteen modes of operations can be explored in one switching cycle and due to fully symmetrical structure, only eight of them are analysed. Figs. 3 and 4 show the equivalent circuit for each mode of operation. Mode 1 : During this time interval, the main switches and conduct and the other semiconductors are in off state. The input voltage charges the magnetising inductances linearly (1) (2) (3) (4) Fig. 1Open in figure viewerPowerPoint Structure of the proposed converter Fig. 2Open in figure viewerPowerPoint Typical waveforms of the proposed converter Fig. 3Open in figure viewerPowerPoint Equivalent circuits of the proposed converter (a) Mode 1, (b) Mode 2, (c) Mode 3, (d) Mode 4 Fig. 4Open in figure viewerPowerPoint Rest of equivalent circuits of the proposed converter (a) Mode 5, (b) Mode 6, (c) Mode 7, (d) Mode 8 Mode 2 : At , switch turns off. The current flows through the parallel capacitor and charges it linearly. Due to , the ZVS turn-off is achieved for (5) Mode 3 : The voltage of increases until it reaches to the clamp capacitor voltage. This makes the antiparallel diode of conduct. Since is much smaller than , most of the current of flows through . At this condition, the voltage across power switch is obtained by (6) Mode 4 : At , the voltage across the switch is large enough to make diodes and conduct. The energy of the magnetising inductor starts transferring to the load via the secondary winding and diode (7) (8) (9) Mode 5 : At , the gate pulse for clamp switch arrives and due to the conductivity of its antiparallel diode, the ZVS turn-on is realised. Mode 6 : At , turns on with ZVS because of the parallel capacitor and . A resonant circuit is formed which makes to start discharging until its voltage reaches to zero. Mode 7 : At , the voltage of reaches zero which makes the antiparallel diode of to turn on (10) (11) (12) Mode 8 : At , the antiparallel diode of is in on state; the gate pulse for comes which provides successful ZVS. During this interval, the leakage inductance current of the built-in transformer starts to decrease and the current of diodes and are decayed to zero. Similar operational modes exist for the next half cycle in which and serve as clamp circuit for power switch . To shorten the steady-state analysis, the parasitic capacitors of the power MOSFETs are neglected. Also, the clamp capacitors and , and the output capacitors , and are considered large enough to neglect their ripple in the whole switching cycle. 3 Steady-state analysis 3.1 Voltage conversion ratio When the main MOSFET is turned on, the magnetising inductance is charged with the input voltage. Also, while the main MOSFET is in OFF state, it is discharged by the voltage of the input source and the voltage of the clamp capacitor. By equating the average voltage across the magnetising inductance, the voltage of clamp capacitors can be obtained by (13) Moreover, according to the third interval, the voltage across the primary winding of the built-in transformers , the primary voltage of the coupled inductors and , and the voltage of the multiplier capacitor can be obtained by (14) (15) (16) (17) Considering (14)–(17), we have (18) (19) Therefore, the output voltage can be calculated as (20) (21) Therefore, the voltage conversion ratio can be expressed by (22) The leakage inductances of the magnetic devices affect the voltage conversion ratio of the proposed converter. The voltage conversion ratio of the proposed convertor considering the leakage inductances is obtained as below: (23) where and . 3.2 Voltage and current stress analysis The voltage stress of the MOSFETs is clamped to the voltage of clamp capacitors and can be obtained as follows: (24) Equation (23) reveals that the voltage stress across the power switches decreases considerably by increasing of the turns ratio of the magnetic means. Therefore, the low voltage power switches with low can be implemented which decreases the cost and improves the performance. The voltage stresses of the diodes are obtained as follows: (25) (26) The RMS and the maximum current of the components are obtained as (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) 3.3 ZVS performance realisation ZVS is realised for all of the MOSFETs during the whole switching cycle. All of the power switches are turned on with ZVS because of the parallel capacitors , , and the clamp capacitors. The clamp switches are naturally turned on with ZVS due to the fact that their antiparallel diodes are conducting before arriving of the gate signals. To realise the ZVS performance for the main switches, the leakage energy of the built-in transformer should be higher than the energy of the parallel capacitors which gives the following equation: (39) 3.4 Analysis of the conduction losses The resistors of the windings of the coupled inductors , , the resistors of the windings of the built-in transformer , , the on-state resistors of the power MOSFETs , the resistors , and the forward voltage drops of the diodes decrease the voltage conversion ratio and the efficiency of the proposed converter. To obtain the voltage conversion ratio under such a condition, the parallel capacitors , and the leakage inductances of the magnetic means are considered zero. The latter one causes to remove the active clamp branches. Fig. 5 shows the equivalent circuit of the proposed converter considering the parasitic components along with the simplified switching pattern. Fig. 5Open in figure viewerPowerPoint Loss distribution of the proposed converter (a) Equivalent circuit for loss analysis, (b) Simplified switching pattern When and are both in ON state, the voltage of the is derived as (40) When is ON and is OFF, we have (41) (42) (43) (44) (45) where (46) When is OFF and is ON, due to symmetry of operation, the voltage across is equal to , which is given as (47) The value of the current through the magnetising inductances and the power diodes are obtained as (48) (49) (50) Introducing the volt-second balance to can be denoted as (51) Through (40)–(51), the voltage gain is derived by (52) where (53) The conversion efficiency is expressed as below: (54) The voltage gain and the conversion efficiency of the proposed converter versus duty cycle and various values of the windings’ resistors are shown in Fig. 6 with the following values: (55) (56) It is seen that the voltage conversion ratio and the conversion efficiency decrease by the duty cycle and various values of the windings’ resistors. Fig. 6Open in figure viewerPowerPoint Voltage gain and efficiency of the proposed converter considering parasitic components 4 Comparison discussion To explore the merits of the proposed converter, a comparison is carried with the various recent published converters in the state-of-the-art that is shown in Table 1. Fig. 7 shows the voltage conversion ratio and the voltage stress comparison of the converters. It is seen that although the proposed converter has higher number of component than some other competitors, however it has the highest voltage conversion ratio, the lowest voltage stress across switching devices and provide ZVS performance. Therefore, the switching devices with the low on-state resistance and low forward voltage drop can be adopted decreasing the overall cost and improve the performance operation. Meanwhile, another main benefit of the proposed converter is that the voltage gain and the voltage stress can be adjusted with the two parameters of n and N. This feature gives an extra degree of freedom to have a more flexible design. To further discuss the advantages of the proposed converter, two non-ZVS converters [25, 30] and two ZVS converters [31, 32] are selected for the comparison of the efficiency, the current stresses of MOSFETs and the magnetic devices’ apparent power. The proposed converter has the value of which yields the voltage gain of . Therefore, to have a wise comparison the turns ratio of is selected for the converters in [25, 32], the turns ratio of , is considered for the converter of [30] and the turns ratio of is chosen for the converter of [31]. The duty cycle is swiped from 50 up to 90% in all comparisons. Moreover, for the voltage conversion of 48–700 V and the output power of 600 W that is similar to the experimented prototype of this paper, the voltage stress of the MOSFETs and diodes are selected. IRFP4227PbF (240 V, 21 mΩ) are chosen for the MOSFETs of the converters. MUR1560 (600 V, 1.3 V) are selected as diodes for the proposed converter and the converters of [25, 30, 31] and MUR480EG (800 V, 1.7 V) is utilised for [32]. Furthermore, the resistances of the windings are considered similar for all of the converters and are equal to the given specifications of the proposed converter in Table 2. The mathematical efficiencies of the competitors are given in Table 3. The efficiencies of the converters are compared in Fig. 8, where Fig. 8a depicts the efficiency versus ideal voltage gain and Fig. 8b illustrates the efficiency versus the real voltage gain by considering the distributed losses. From Fig. 8a, it is seen that the proposed converter has the highest efficiency and the converter of [25] has the lowest efficiency at a similar ideal voltage gain. Meanwhile, from Fig. 8b it is clear that while the duty cycle is increased up to 90%, the voltage gain of the proposed converter is the highest and the it is severely decreased for the converters of [25, 30-32]. The RMS and maximum currents of the MOSFETs are given in Table 4 that are plotted versus voltage gain in Fig. 9. It is seen that at a given voltage gain, the MOSFETs tolerate relatively similar RMS current in all competitors and the maximum current stress in the converter of [30] is the lowest. The handled apparent power of the magnetic devices is a factor for comparison of the volume of the cores that are given in Table 5 for all of the competitors. The converter of [25] has two coupled inductors, the proposed converter and the converter of [30] utilise two coupled inductor and a built-in transformer, and the converters of [31, 32] serve two inductors and a built-in transformer. The primary of the coupled inductors serves the same role as the input inductor of the conventional boost converter similar to the converters of [31, 32]. Fig. 10 shows the comparison of the apparent power of magnetic devices. The built-in transformer in the proposed converter has the lowest apparent power for the voltage gains higher than 23 and for lower voltage gains the one in [30] has the lowest value. The input inductors in [31, 32] has the lowest apparent power and the coupled inductors in [25] handle the highest value. It is concluded that the proposed converter has the advantages of high voltage gain, low voltage stress across switching devices, high efficiency, low current stress and low handled apparent power for magnetic devices. Hence, the proposed converter can be regarded as a suitable candidate for high step-up applications. Fig. 7Open in figure viewerPowerPoint Comparison discussion (a) Voltage gain, (b) Normalised voltage stress across the MOSFETs, (c) Normalised voltages stress across diodes Fig. 8Open in figure viewerPowerPoint Comparison of conversion efficiency (a) Versus ideal voltage gain, (b) Versus real voltage gain Fig. 9Open in figure viewerPowerPoint Comparison of the current stresses of MOSFETs Fig. 10Open in figure viewerPowerPoint Apparent power comparison of the magnetic devices Table 1. Performance comparison of the proposed converter with the interleaved existing converters Converters Technique Number of components ZVS MOSFET Diode Capacitor Core Total Ref. [20] CI* + VMC 2 8 7 2 19 no Ref. [21] CI* + VMC 2 6 5 2 15 no Ref. [22] BIT* + VMC 2 6 5 3 16 no Ref. [23] BIT* + VMC 1 2 4 3 3 12 no Ref. [24] CI* + VMC 2 4 4 2 12 no Ref. [25] CI* + VMC 2 6 5 2 15 no Ref. [30] CI* + BIT* + VMC 2 6 5 3 16 no Ref. [31] BIT* + VMC 4 4 3 3 14 yes Ref. [32] BIT* + VMC 1 4 4 5 3 16 yes Ref. [36] CI* + VMC 4 6 7 4 21 yes Ref. [37] CI* + VMC 3 10 6 3 22 yes proposed CI* + BIT* + VMC 4 6 7 3 20 yes CI: coupled inductor; BIT: built-in transformer. Table 2. Specifications of the proposed converter Components Parameters output power input–output voltages 48–700 V switching frequency power MOSFTEs diodes and MUR1560-MUR1540 parallel capacitors (CS 1, CS 2) 2 nF capacitors capacitors capacitor coupled inductors built-in transformer Table 3. Mathematical efficiencies of the converters introduced in [25, 30-32] and the proposed converter Converter Efficiency [25] [30] [31] [32] , proposed (54) Table 4. Current stress comparison Converter RMS and maximum currents of the MOSFETs (M is voltage gain) [25] [30] [31] [32] proposed (27) and (36) Table 5. Comparison of magnetic devices’ apparent power Converter Apparent power of the magnetic devices [25] [30] [31, 32] proposed (63) and (64) 5 Design considerations 5.1 Design of magnetic devices By determining the duty cycle, the input voltage and the output voltage, the turns ratios of the magnetic devices are selected such as to satisfy the following equation: (57) is designed based on (39) to achieve successful ZVS. To ensure the continuous conduction mode (CCM) operation, the magnetising inductances are designed as follows: (58) After designing the required value of for CCM operation, the value of can be obtained by (59) where is the maximum current of the magnetising inductance, is the maximum of the magnetic flux density and denotes the cross-sectional area of the core. Also, from the obtained values of n and np in (57) and (59), the value of is yield. When is ON and is OFF, the primary side voltage of the built-in transformer can be written as (60) where denotes the swing of the magnetic flux density. From (60), is derived and consequently using (57), the values of are obtained. The value of RMS currents flowing through the windings of the magnetic devices are calculated from (30)–(33), and then the proper diameters of the wires can be calculated. The RMS voltages across the primary sides of the magnetic devices can be derived from (61) (62) Equations (30), (31) and (61), (62) yield the apparent power of the magnetic devices as below: (63) (64) 5.2 Design of switching devices The MOSFETs and diodes are easily designed from stress analyses in (24)–(29) and (36)–(38). 5.3 Design of capacitors After specifying the desired voltage ripple of the capacitors, their capacitance can be obtained by (65) (66) where and are the voltage ripples of and , respectively. 6 Experimental results To verify the carried steady-state analysis and the performance operation, the proposed converter is built with 600 W output power and 48–700 V voltage conversion. The picture of the experimented prototype and the components specifications are shown in Fig. 11 and Table 2, respectively. Fig. 11Open in figure viewerPowerPoint Picture of the experimented prototype Fig. 12a depicts the output voltage and the output current. The high output voltage of 700 V is obtained due to contribution of the turns ratios of the magnetic devices at moderate duty cycle of 60%. Fig. 12Open in figure viewerPowerPoint Experimental measurements of (a) Output voltage and current, (b) Voltage and current of MOSFET S 1, (c) Voltage and current of SC 1 Fig. 12b shows the current and the voltage of the main switch . The voltage across the MOSFET falls to zero before applying of the turn-on pulse and the ZVS performance is realised. Also, the voltage stress is effectively clamped to 115 V that is substantially lower than the high output voltage. Hence, the low voltage rated MOSFETs can be adopted decreasing the conduction losses and improves the operation of the proposed converter. Fig. 12c shows the current and the voltage of the clamp switch . The turn-on ZVS performance is achieved for the clamp MOSFET and its drain–source voltage is clamp to 115 V which is equal to that of the main MOSFET . Figs. 13a –c show the experimental currents and voltages of the implemented diodes. The voltage stresses of the diode match with the mathematical analysis and are substantially lower than the high output voltage. Hence, diodes with lower on-state resistance and forward voltage drops can be utilised decreasing the conduction losses and cost. Meanwhile, ZCS turn-off performance is realised for all of the diodes and the reverse recovery problem is solved. Fig. 13d depicts the experimental result of the input current and the leakage inductances of the coupled inductors. It is clear that the ripple of the input current is minimised to the interleaving effect and the input current is shared between the phases. Fig. 13Open in figure viewerPowerPoint Experimental measurements of (a) Voltage and current of diode D 1, (b) Voltage and current of diode Db 1, (c) Voltage and current of diode Df 1, (d) Input current and the currents of the leakage inductances of the coupled inductors The measured conversion efficiency of the proposed converter versus various output power is shown in Fig. 14. The maximum efficiency of 97.3% is achieved at 500 W output power and the full load efficiency is 97%. Fig. 14Open in figure viewerPowerPoint Measured efficiency of the proposed converter The losses distribution of the proposed converter at the 500 and 600 W output powers is given in Table 6. The values of the parasitic resistances and the forward voltage drops of the diodes are based on the experimental prototype in Table 2. It is seen that the mathematical conversion efficiency of the proposed converter under 500 and 600 W output power are about 98.55 and 98.38%, respectively, that are consistent with the experimental efficiency of Fig. 14. It is worth to mention that the differences between the measured and mathematical efficiencies are due to the prototype layout and the core losses that are not considered in the analysis. Table 6. Losses distribution of the proposed converter Output power 500 W 600 W ((27)) 6.75 A 8.1 A ((28)) 1.95 A 2.35 A 1.97 W 2.84 W ((29)) 0.65 A 0.78 A 0.36 A 0.43 A 3.19 W 3.84 W ((30)) 5.53 A 6.63 A ((32)) 1.84 A 2.21 A 1.83 W 2.64 W ((31)) 1.84 A 2.21 A ((33)) 0.92 A 1.11 A 0.2 W 0.3 W 2 W 2.93 W ((28)) 1.96 A 2.35 A ((33)) 0.92 A 1.11 A ((34)) 0.58 A 0.7 A ((35)) 1.09 A 1.31 A 0.16 W 0.23 W 7.36 W 9.85 W efficiency 98.55% 98.38% 7 Conclusion An interleaved high step-up ZVS DC-DC converter with coupled inductor and built-in transformer VMC has been introduced in this paper. High voltage conversion ratio and minimised voltage stress on the semiconductors are achieved by the turns ratios of the magnetic devices which results in a more flexible design in comparison with the converters with only one of these magnetic means. Through active clamp circuits, the ZVS performance are realised for the MOSFETs in the whole switching period that enables the proposed converter to be operated at the high frequency of 100 kHz while maintaining the high efficiency. The imposed voltage on the MOSFETs is substantially lower than the output voltage and the voltage stress across the diodes is lower than the high output voltage. Hence, the low voltage rated semiconductors can be used which decreases the on-state losses and improves performance operation. Meanwhile, the leakage inductances of the magnetic means provide ZCS turn-off for the power diodes and the reverse current recovery problem is solved. On the other hand, because of the interleaved architecture, the ripple of the input current is minimised that is a crucial point for PV and FC applications. Experimental verification of a 600 W, 48–700 V laboratory prototype with 97% conversion efficiency at full load effectively presents the satisfactory operation of the proposed converter. Motivated by the advantages of the proposed converter, it can be regarded as a suitable alternative for high voltage and high power applications such as sustainable energy systems. 8 References 1Forouzesh M. Siwakoti Y. P. Gorji S. et al.: ‘Step-up DC-DC converters: A comprehensive review of voltage-boosting techniques, topologies, and applications’, IEEE Trans. Power Electron., 2017, 32, (12), pp. 9143– 9178 2Zhu X. Zhang B. Li Z. et al.: ‘Extended switched-boost DC-DC converters adopting switched-capacitor/switched- inductor cells for high step-up conversion’, IEEE J. Emerg. Sel. Top. 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