Design of an Asynchronous eFuse One-Time Programmable Memory IP of 1 Kilo Bits Based on a Logic Process
2009; Volume: 13; Issue: 7 Linguagem: Inglês
ISSN
2288-4165
AutoresJae‐Hyung Lee, Min-Cheol Kang, Liyan Jin, Ji-Hye Jang, Pan-Bong Ha, Young‐Hee Kim,
Tópico(s)Advanced Memory and Neural Computing
ResumoWe propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5A and 3.3A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18m generic process is 300 557.
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