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Low-voltage single supply CMOS electrically erasable read-only memory

1980; Institute of Electrical and Electronics Engineers; Volume: 27; Issue: 7 Linguagem: Inglês

10.1109/t-ed.1980.20010

1557-9646

B. Gerber, J. Fellrath,

Advancements in Semiconductor Devices and Circuit Design

A low-voltage single supply CMOS electrically erasable read-only memory (CMOS-EEROM) is described. It combines long-term charge retention and the possibility of being read, written, and erased from a single power supply. Negative write and erase voltages are generated on-chip by voltage multipliers. It is shown that writing by avalanche injection and erasing by Fowler-Nordheim emission, are compatible with the low power output associated with these multipliers. In order to reduce the programming voltages below 40 V, injection oxide thickness is locally reduced by one additional photolithographic step compared to conventional silicon-gate CMOS technology. The influence of this oxide thickness and of polysilicon doping on write and erase characteristics, endurance, and charge retention are analyzed.