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An eight‐switch five‐level inverter with zero leakage current

2020; Institution of Engineering and Technology; Volume: 14; Issue: 3 Linguagem: Inglês

10.1049/pel2.12041

1755-4543

Sangeeta Kumari, Arun Kumar Verma, N. Sandeep, Udaykumar R. Yaragatti, H. R. Pota,

Advanced DC-DC Converters

IET Power ElectronicsVolume 14, Issue 3 p. 590-601 ORIGINAL RESEARCH PAPEROpen Access An eight-switch five-level inverter with zero leakage current Sangeeta Kumari, Corresponding Author Sangeeta Kumari 2018ree9504@mnit.ac.in orcid.org/0000-0002-0220-2218 Department of Electrical Engineering, Malaviya National Institute of Technology, Jaipur, India Correspondence Sangeeta Kumari, Department of Electrical Engineering, Malaviya National Institute of Technology, Jaipur, India. Email: 2018ree9504@mnit.ac.inSearch for more papers by this authorArun Kumar Verma, Arun Kumar Verma Department of Electrical Engineering, Malaviya National Institute of Technology, Jaipur, IndiaSearch for more papers by this authorSandeep N, Sandeep N orcid.org/0000-0002-2670-2049 Department of Electrical Engineering, Malaviya National Institute of Technology, Jaipur, IndiaSearch for more papers by this authorUdaykumar R. Yaragatti, Udaykumar R. Yaragatti Department of Electrical Engineering, Malaviya National Institute of Technology, Jaipur, IndiaSearch for more papers by this authorHemanshu Roy Pota, Hemanshu Roy Pota School of Engineering and Information Technology, The University of New South Wales, AustraliaSearch for more papers by this author Sangeeta Kumari, Corresponding Author Sangeeta Kumari 2018ree9504@mnit.ac.in orcid.org/0000-0002-0220-2218 Department of Electrical Engineering, Malaviya National Institute of Technology, Jaipur, India Correspondence Sangeeta Kumari, Department of Electrical Engineering, Malaviya National Institute of Technology, Jaipur, India. Email: 2018ree9504@mnit.ac.inSearch for more papers by this authorArun Kumar Verma, Arun Kumar Verma Department of Electrical Engineering, Malaviya National Institute of Technology, Jaipur, IndiaSearch for more papers by this authorSandeep N, Sandeep N orcid.org/0000-0002-2670-2049 Department of Electrical Engineering, Malaviya National Institute of Technology, Jaipur, IndiaSearch for more papers by this authorUdaykumar R. Yaragatti, Udaykumar R. Yaragatti Department of Electrical Engineering, Malaviya National Institute of Technology, Jaipur, IndiaSearch for more papers by this authorHemanshu Roy Pota, Hemanshu Roy Pota School of Engineering and Information Technology, The University of New South Wales, AustraliaSearch for more papers by this author First published: 29 December 2020 https://doi.org/10.1049/pel2.12041Citations: 9AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract This paper examines a multilevel transformer-less grid-tied inverter topology is proposed for PV applications. Nowadays, transformer-less inverters are more desirous due to their small filter size, cheaper and higher efficiency. However, the removal of transformer results in the existence of leakage current due to absence of galvanic isolation. The flow of leakage current is the cause of personal safety and deteriorating power quality. A transformer-less inverter topology is proposed which is able to solve the leakage current issue. Besides, it has the ability to generate the boosted voltage without the need of magnetic component or boosting circuit. It works on the principle of flying/switched capacitor which are able to naturally balance the voltage. Hence, it does not have the limitation of modulation index and no need of complex control scheme to balance or regulate the voltage across an auxiliary capacitor. The performance of the proposed topology is verified by implementing a laboratory prototype which validates the operation and performance of the proposed topology. Results depicting the output voltage, load current and voltage across the auxiliary capacitor are presented for various operating conditions. Moreover, a comprehensive comparison is done, in terms of component count, level and boosting ability of output voltage with leakage current condition. 1 INTRODUCTION Rapid increase in electricity demand has been a challenge to the costly oil, climate changes and depleting fossil fuel. As a result, to fulfil the electricity demand generation from renewable energy sources is continuously increasing. Among all renewable energies photovoltaic (PV) production have exponential hike in industrial and residential application. In the grid-tied PV systems power electronic converters are a very important part for the integration of PV sources into the power grid. These converters are generally classified as galvanic-isolated and non-isolated system. Transformers are connected on the ac or dc side of the inverter which provides the galvanic isolation. AC side transformers have low frequency, hence they are big in size, lower efficiency, high in cost and tough to install. Whereas, high frequency transformers results in smaller in size and cheaper while energy conversion stages (dc-dc and dc-ac) are more which leads to decreased efficiency and increased complexity of the system as compared to ac side transformer. Therefore, in renewable energy application transformer-less grid-tied inverters are more beneficial [1, 2] due to their small size, low cost and higher efficiency. Absence of transformer results leads to the flow of leakage current between PV-to-grid [3-5]. The leakage current injects the harmonics in the grid current, causes personal safety problems, electromagnetic interference (EMI) and increased system losses. Hence it is necessary to eliminate the leakage current and lot of transformer-less inverter topologies have been proposed previously. By maintaining a constant common mode (CM) voltage leakage current can be minimized. In order to reduce a common mode voltage various proposed topologies are based on the conventional H-bridge inverter, such as H-5 [6, 7], H-6 [8], HERIC inverters families [9] etc. As shown in Figure 1(a), H-5 inverter has one additional which is connected between dc-bus and h-bridge. Whereas, H-6 inverter has two extra switches which are inserted in the middle of dc-bus terminals and bridge arms, as depicted in Figure 1(b). HERIC based topologies have freewheeling branch which is inserted between h-bridge output terminal and load side filters, as depicted in Figure 1(c). These additional switches and branches are inserted for isolating the path from PV array to utility grid during freewheeling mode. For such topologies, it is very difficult to reduce the leakage current due to parasitic capacitance of switches. In addition, these inverters need two filter inductors results in increased size and expensive [10]. Moreover, conduction losses are high due to more than three conducting switches in series during active mode [11]. Another H-Bridge based five-level inverter proposed in [12], it consists of eight switches, two flying capacitors, one diode and two filter inductors. Additionally, one five-level topology is presented in [13], which made of six switches, two flying capacitors and two filter inductors. Again these topologies are not able to generate the boosted voltage. FIGURE 1Open in figure viewerPowerPoint H-Bridge based transformer-less grid-tied inverter topologies (a) H-5 [7] (b) H-6 [8] (c) HERIC [9] Other topologies are based on the half-bridge, where middle-point of the dc-bus tied with utility neutral, as shown in Figure 2(a) [14]. These topologies reduces the leakage current with single filter inductor while the required input voltage is twice of the generated output [15]. Another variant namely active NPC (ANPC) inverter is the popular version of NPC where in the passive diodes are substituted with the active switches [16]. Hence, additional boosting circuit is required to meet the grid voltage requirement. Which results in extra power conversion stage, hence efficiency is decreased and increased cost [16]. Additionally, efforts are made to integrate the boosting feature in to the inverter without much consideration to the issue of ground leakage current [17, 18]. FIGURE 2Open in figure viewerPowerPoint (a) Half-Bridge inverter [14] (b) Karschny Inverter [20] (c) CGT Based Topology [21] Recently, a popular is proposed in the literature which are common ground type (CGT) inverter topologies [19] and are shown in Figure 2. As compared to other available inverter topologies, CGT based inverter is able to eliminate the leakage current completely due to short-circuiting of PV-to-ground parasitic capacitance. Karschny transformer-less inverter is also CGT based, which consists of five power semi-conductor switches, two diodes, one storage and one filter inductors with one capacitor. The circuit diagram of karschny transformer-less inverter, as depicted in Figure 2(b) [20] is very complicated and needs sophisticated control structure and also it is not able to deliver the reactive power to the power grid. The virtual dc-bus inverter is based on the concept of utilizing the intermediate charged capacitor for the generation of negative voltage levels. A switched-capacitor is used for the creation of virtual dc-bus. The achievable peak output voltage is the same as input dc-link voltage like in the case of the conventional full-bridge inverter. The virtual dc-bus inverter, as shown in Figure 2(c) [21] consists of five switches, two capacitors, single filter inductors and reduced/zero ground leakage current. Another CGT based topology is presented in [22], which suppresses the leakage current completely while it is incapable to generate the boosted voltage. Another, five-level inverter is presented in [23] based on CGT, reduces the count of components and eliminates the leakage current but again is incapable to generate the boosted output voltage. Further, CGT based single phase inverter topology is proposed in [24] which works on the principle of flying capacitor. It is constructed with four switches, one diode, one flying capacitor and filter inductor is also one. The beneficial feature of this topology is that during the power transfer mode, the maximum number of on state switches is 2, leads to improved efficiency. The above discussed topologies are able to eliminate the leakage current but incapable to generate a boosted output voltage. Other concerns is, auxiliary capacitors charging and discharging operation and balanced voltage at a desired level. In practical applications, it is desirous to generate multilevel voltage in order to reduce the filter size, reduce voltage stress and increase efficiency. Hence, with the increased number of voltage levels count of auxiliary capacitors is also increases which leads to more number of required sensor and circuit becomes costly. Another CGT based five-level inverter topology presented in [25], yields in zero leakage current. It consists of six switches, one diode, two flying capacitor and a single inductor with no voltage boosting ability. Also, it requires voltage and current sensors which leads to increased cost. Other CGT based five-level topology in [26], consists of nine switches, two flying capacitor and a single inductor. Recently, boosting inverter topologies are proposed in [27, 28]. Despite many efforts toward the topological advancement has been made, still there exists a huge scope for synthesizing of reduced component based CGT topology with boosting ability. This paper examines a transformer-less grid-tied inverter topology is proposed which is common ground type (CGT), where the ground of utility is connected with the negative terminal of dc source. This results in a short circuit of PV-to-ground parasitic capacitance leads to complete elimination of the CM leakage current. It has the ability of inherent boosting voltage without any additional circuit. The proposed inverter topology generates five-level output voltage leads to minimized voltage stress, decreased filter size and higher efficiency. Auxiliary capacitors are naturally balanced, hence proposed topology does not have any limitation on the achievable modulation index. Maximum conducting switch in the grid current path is ⩽ 3 during the energy transmission mode, which results in increased efficiency. The major contribution of the presented work is the devising of a five-level inverter with zero leakage current with reduced component count for PV application. The paper is organized as follows: structure and operating modes of the proposed inverter topology are explained in Section II. Common mode behaviour is elucidated in Section III. Sections IV and V describes the design guidelines and power loss analysis. A quantitative comparison of existing grid-tied inverter topologies with proposed inverter is done in Section VI. Experimental results of are explained to validate the feasibility of the presented topology in Section VII. Finally, the paper is concluded in the following section. 2 STRUCTURE OF THE PROPOSED INVERTER TOPOLOGY 2.1 Structural description of the proposed five-level boosted inverter topology The schematic of the proposed topology is shown in Figure 3. It consists of seven power switches, two auxiliary capacitors and one diode for synthesizing a five-level output voltage waveform. The appropriate switching states to be employed are listed in Table 1. The switches S ¯ 1 , S ¯ 2 and S ¯ 3 work in complementary to switches S1, S2 and S3 respectively. The input voltage is designated as V d c . The auxiliary capacitor C2 helps to generate the negative levels of the output voltage. Voltage across the auxiliary capacitors C1 and C2 are to be maintained at V d c and 2 V d c respectively to produce five-level voltage. TABLE 1. States of the switches (↑ : Charging, ↓ : discharging ) V o u t S1 S2 S3 S B D C1 C2 2 V d c on on on on off ↓ ↑ V d c off on on off on ↑ - 0 on on off on off ↓ ↑ − V d c off on off off on ↑ ↓ − 2 V d c off off off off on ↑ ↓ FIGURE 3Open in figure viewerPowerPoint Schematic of the proposed inverter topology with boosting ability 2.2 Analysis of operating modes Working modes of the proposed inverter topology are shown in Figure 4. The proposed topology has five working modes, as per the direction of output voltage, current and level of output voltage. The figure describes the switching state of switches, charging/discharging structure of auxiliary capacitors and output-current path. The different working modes are analyzed in details as follows. FIGURE 4Open in figure viewerPowerPoint Working modes of operation (Red and green lines shows the current direction for upf and non-upf respectively) Mode I: i g > 0 , V o u t > 0 . In this mode, power is transferred from PV to grid side through S1, S2 and S3 , as shown in Figure 4. The auxiliary capacitor C2 charges from the source and C1 up to 2 V d c through S1, S2 and S B over the whole period. Mathematically, the output voltage can be expressed as: V o u t = V d c + V c 1 = 2 V d c , i g > 0 (1)During this operating mode inductor current ( i L ) increases rapidly passing through grid and is expressed as: i L = 2 V d c − V g L f . (2)Mode II: i g > 0 , V o u t > 0 . In this mode, power is transferred from auxiliary capacitor C1 to grid side through S 1 ¯ , S2 and S3, as shown in Figure 4. The auxiliary capacitor C1 charges from the source up to V d c through diode and S 1 ¯ over the whole period, C2 is disconnected and its voltage remains intact. Mathematically, the generated voltage can be expressed as: V o u t = V c 1 = V d c , i g > 0 (3)and inductor current ( i L ) is expressed as: i L = V d c − V g L f (4)Mode III: i g > 0 or 0 or < 0 . (5)During this mode i L passes through S 3 ¯ and S B and linearly decreases, is expressed as: i L = − V g L f . (6)Mode IV: i g < 0 , V o u t < 0 . In this mode, energy is transferred from grid to dc side through S 3 ¯ , S2 and S 1 ¯ , as shown in Figure 4. For positive load current the auxiliary capacitor C2 discharges to C1 and grid while for negative load current, vice-versa over the whole period. Mathematically, the generated voltage can be expressed as: V o u t = V c 2 − V c 1 = − V d c , i g < 0 . (7)During this operating mode i L increases rapidly in reverse direction passing through grid, expressed as: i L = V d c − V g L f . (8)Mode V: i g < 0 , V o u t < 0 . In this mode, energy is transferred from auxiliary capacitor C2 to the grid side through S 1 ¯ and S 2 ¯ , as shown in Figure 4. The auxiliary capacitor C1 charges from the source up to V d c through diode and S 1 ¯ over the whole period. Mathematically, the generated voltage can be expressed as: V o u t = V c 2 = − 2 V d c , i g < 0 . (9)During this mode i L passes through C2, S 3 ¯ and S 2 ¯ , which is expressed as: i L = 2 V d c − V g L f L . (10)These working modes are analyzed and if the load requires reactive power then charging/discharging structure of auxiliary capacitors are varied according to load current direction, as shown in Figure 4. 2.3 Pulse-width modulation scheme This section describes the gating-signals for each switch, which is developed by using logic gates and comparators. A sinusoidal reference signal ( V r e f ) is compared with carrier signals which are V c r 1 , V c r 2 , V c r 3 and V c r 4 , as depicted in Figure 5. Logic function is developed for all switches to perform the desirous operation according to the operating modes demonstrated in Section II. The rationale behind the logic operation involves those entries wherein a particular switch needs to be ON. For example, consider for S1, since it is ON for zero and 2 V d c level, the comparator outputs corresponding to these two levels are added (logical OR). Using the same principle the logic expression for rest of the switches have been derived. FIGURE 5Open in figure viewerPowerPoint Logical functions to synthesize gate pulses 3 COMMON MODE BEHAVIOUR By maintaining a constant CM voltage, ground leakage current is minimized/eliminated. In this section the capability of proposed topology in maintaining a constant CM voltage by considering the effect of the parasitic capacitor of switches is illustrated. The equivalent circuit during mode I and II by considering the parasitic capacitors of switches, is demonstrated in Figure 6. According to the equivalent circuit of mode I, shown in Figure 6(a) the voltage at point A with respect to point N is: V A N = 2 V d c (11) V B N = 0 . (12)The total CM voltage V c m − a l l is expressed by [9]: V c m − a l l = V A N + V B N 2 + ( V A N − V B N ) L 2 − L 1 2 ( L 2 + L 1 ) = 2 V d c + 0 2 + ( 2 V d c − 0 ) 0 − L 2 ( 0 + L ) = 0 . (13)As per circuit equivalent circuit of mode II, shown in Figure 6(b) the voltage V A N is given by: V A N = V d c (14) V B N = 0 . (15)Further the CM voltage is expressed by: V c m − a l l = V d c + 0 2 + ( V d c − 0 ) 0 − L 2 ( 0 + L ) = V d c 2 − V d c 2 = 0 (16)where V A N and V B N is voltage between the phase A and point N, phase B and the point N, respectively as shown in Figure 6 and C P V capacitor between PV neutral and grid neutral. The ground leakage current is expressed as: i c m = C P V d V c m − a l l d t = 0 . (17)Since, the CM voltage is effected by the presence of switch parasitic capacitance of switches, hence the proposed topology is able to eliminate the ground leakage current completely. FIGURE 6Open in figure viewerPowerPoint Equivalent circuit with parasitic capacitor during (a) Mode I (b) Mode II 4 DESIGN GUIDELINE In this section, the methodology and relevant mathematical expressions to calculate the component values used in the proposed topology are presented. The output voltage during zone I as shown in Figure 5 is defined as: V 0 = 2 V d c 0 < t < D T s V d c D T s < t < T s . (18)Therefore, voltage across filter inductor is defined as: V L = 2 V d c − V g 0 < t < D T s V d c − V g D T s < t < T s . (19)By using the volt-second balance principle: ∫ 0 D T s ( 2 V d c − V g ) d ( t ) + ∫ D T s T s ( V d c − V g ) d ( t ) = 0 (20)solving (30) yields duty ratio (D) as, D = V g V d c − 1 . (21) 4.1 Inductance value The passing current of filter inductor within a complete switching cycle is obtained as i L ( t ) = 1 L f ∫ 0 t V L ( t ) d ( t ) + i L ( 0 ) . (22)Hence, ripple current of the inductor is obtained as: Δ i L = ( 2 V d c − V g ) D T s L f . (23)By using (31) in (23), it ripple current is: Δ i L = 1 L f f s 2 V d c − 3 V g + V g 2 V d c . (24)So, L can be calculated as: L f = 1 Δ i L f s 3 V g − V g 2 V d c − 2 V d c . (25) 4.2 capacitance value For sizing of the auxiliary capacitors value, following equation is used - C 1 = i g ∗ Δ t Δ V C ∗ V C 1 (26)where i g is the load peak current, Δ t is charging or discharging time for capacitor, V C is the voltage for capacitors i.e. V d c for C1 and 2 V d c for C2 and Δ V C is the % of maximum ripple content in capacitor voltage. During 2V0 = 2 V d c , Δ t is D T s , hence C 1 = i g D T s Δ V C ∗ V d c = i g f s Δ V C ∗ V d c V g V d c − 1 . (27) 5 LOSS CALCULATION AND ANALYSIS In the practical applications semi-conductor switches has energy losses, which includes conduction and switching losses. These losses occur due to their turning on/off time, passing active current, their blocking voltage and ON-state resistance. 5.1 Zone I The output voltage during zone I as shown in Figure 5 is defined as: V 0 = 2 V d c 0 < t < D 1 T s V d c D 1 T s < t < T s . (28)Therefore, voltage across filter inductor is defined as: V L = 2 V d c − V g 0 < t < D 1 T s V d c − V g D 1 T s < t < T s . (29)By using the volt-second balance principle: ∫ 0 D 1 T s ( 2 V d c − V g ) d ( t ) + ∫ D 1 T s T s ( V d c − V g ) d ( t ) = 0 . (30)solving (30) yields duty ratio (D1) as, D 1 = V g ( t ) V d c − 1 . (31) 1. Conduction loss: Average conduction loss for a switch could be expressed as: P c o n d . = 1 2 π ∫ 0 π i s ( t ) v s ( t ) D s ( t ) d ( ω t ) (32)where i s 1 , 2 ( t ) = I m s i n ω t + I c , i s 3 ( t ) = I m s i n ω t and i s B ( t ) = I c . Voltage across switches is v s ( t ) = i s ( t ) R d s , v g ( t ) = v m s i n ω t and D s ( t ) = ( V g ( t ) V d c − 1 ) . I c passing current through flying capacitor C2, I c = C 2 d V C 2 d t . Conduction loss for switch S1 and S2 P c o n d . 1 , 2 is expressed as: P c o n d . 1 = 1 2 π × ∫ 0 π ( I m s i n ω t + I c ) ( I m s i n ω t + I c ) R d s v m s i n ω t V d c − 1 d ( ω t ) . (33) By solving this equation conduction loss for switch S1 and S2 is calculated as: P c o n d . 1 = 2 I m 2 3 π v m v d c − 1 + I C 2 v m π v d c − 1 2 + I m I c v m 2 v d c − 2 π R d s . (34) Conduction loss for switch S3 P c o n d . 3 is expressed as: P c o n d . 3 = 1 2 π ∫ 0 π I m 2 R d s s i n 2 ω t v m s i n ω t V d c − 1 d ( ω t ) . (35)Using the above equation the conduction loss for switch S3 is obtained as: P c o n d . 3 = I m 2 2 π R d s 4 v m 3 V d c − π 2 . (36) Conduction loss for switch S B P c o n d . B is expressed as: P c o n d . B = 1 2 π ∫ 0 π I C 2 R d s v m s i n ω t V d c − 1 d ( ω t ) . (37)The conduction loss for switch S B is obtained as: P c o n d . B = I C 2 2 π R d s 2 v m V d c − π . (38) Switches S ¯ 2 and S ¯ 3 both are off, hence conduction loss for these switches are zero during zone I. 2. Switching loss: Generally, switching losses occur due to cross over of voltage and current waveform at the time of commutation, which can be expressed as: P s w = f s 1 6 ∫ 0 t o n v s b ∗ I s a v g d ( t ) + ∫ 0 t o f f v s b ∗ I s a v g d ( t ) . (39) Switching loss for switch S1 During zone I, passing current of S1 is: During zone I, a i S 1 a v g = I m π + I c 0 < t < D 1 T s 0 D 1 T s < t < T s (40)verage of passing current of S1 calculated as: I s 1 a v g = 1 T s ∫ 0 D 1 T s I m π + I c d ( t ) = I m π + I c D 1 (41) i s ( t ) = I m s i n ω t , Hence i s a v g = I m π . And blocking voltage of S1 is V d c , hence switching losses is obtained as: P s w 1 = f s 1 6 [ ∫ 0 t o n V d c ∗ I m π + I c D 1 d ( t ) (42) + ∫ 0 t o f f V d c ∗ I m π + I c D 1 d ( t ) ] (43) = f s V d c I m π + I c D 2 6 ( t o n + t o f f ) . (44) Switching loss for switch S B During zone I, average of passing current of S B calculated as: I s B a v g = I C D 1 . (45)And blocking voltage of S B is 2 V d c , hence switching losses is obtained as: P s w B = f s 1 6 ∫ 0 t o n 2 V d c ∗ I C D 1 d ( t ) + ∫ 0 t o f f 2 V d c ∗ I C D 1 d ( t ) (46) = f s V d c I C D 1 3 π ( t o n + t o f f ) . (47) Switches S2 and S3 both are on, S ¯ 2 and S ¯ 3 both are off during zone I, hence switching for these switches are zero. By applying a similar methodology for the remaining zones, conduction and switching losses are obtained. 5.2 Junction temperature The effective junction temperature for a switching device is expressed as [29, 30]: T j = T A + P T o t ∗ R j θ (48)where T A is ambient temperature, P T o t is total power loss which is P c o n d . + P s w and R j θ junction thermal impedance. Junction temperature for switch S1 is obtained as: T j = T A + ( P c o n d . 1 + P s w 1 ) ∗ R j θ . (49)If R j θ is 40 °C/W and power loss across S1 is 1.15 W, T j is obtained as : T j = 25 + 1.15 ∗ 40 = 71 ∘ C . (50) Hence S1 is able to sustain the 71 ° C junction temperature. 6 COMPARISON WITH OTHER SIMILAR TOPOLOGIES A comprehensive yet qualitative comparison of the proposed topology against the state-of-the-art inverters is carried out in this section. Table 3 summarizes the different figures of merits considered for the comparative study. The comparison is done in terms of component count, on-state switches during each mode, existence of leakage current, levels and boosting ability of output voltage. The number of power switches is a critical feature in inverters to dictate the overall size and cost. The more number of switches escalates the cost, size and complexity of the circuit, while the number of conducting switches affects the overall conduction and switching losses, and in turn the efficiency of the inverter. From the literature survey, it can be seen that the topologies based on the half-bridge inverter requires twice the peak grid voltage. None of them have the boosting ability, hence additional conversion circuit is needed to fulfil the grid voltage requirement. To overcome all problems the topology is proposed in this paper which all merits that are desirous. TABLE 2. Losses During Zone I Switch Blocking Voltage Switching loss Conduction loss S1 V d c f s V d c I m π + I c D 2 6 ( t o n + t o f f ) 2 I m