Interleaved non‐isolated DC–DC converter for ultra‐high step‐up applications
2020; Institution of Engineering and Technology; Volume: 13; Issue: 18 Linguagem: Inglês
10.1049/iet-pel.2020.0285
ISSN1755-4543
AutoresRezvan Fani, Ebrahim Farshidi, Ehsan Adib, Abdolnabi Kosarian,
Tópico(s)Multilevel Inverters and Converters
ResumoIET Power ElectronicsVolume 13, Issue 18 p. 4261-4269 Research ArticleFree Access Interleaved non-isolated DC–DC converter for ultra-high step-up applications Rezvan Fani, Corresponding Author Rezvan Fani r.fani@shhut.ac.ir Department of Electrical, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran Department of Electrical Engineering, Shohadaye Hoveizeh University of Technology, Dasht-e Azadegan, Khuzestan, IranSearch for more papers by this authorEbrahim Farshidi, Ebrahim Farshidi Department of Electrical, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, IranSearch for more papers by this authorEhsan Adib, Ehsan Adib Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, IranSearch for more papers by this authorAbdolnabi Kosarian, Abdolnabi Kosarian Department of Electrical, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, IranSearch for more papers by this author Rezvan Fani, Corresponding Author Rezvan Fani r.fani@shhut.ac.ir Department of Electrical, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran Department of Electrical Engineering, Shohadaye Hoveizeh University of Technology, Dasht-e Azadegan, Khuzestan, IranSearch for more papers by this authorEbrahim Farshidi, Ebrahim Farshidi Department of Electrical, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, IranSearch for more papers by this authorEhsan Adib, Ehsan Adib Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, IranSearch for more papers by this authorAbdolnabi Kosarian, Abdolnabi Kosarian Department of Electrical, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, IranSearch for more papers by this author First published: 17 February 2021 https://doi.org/10.1049/iet-pel.2020.0285Citations: 6AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract This study presents a novel interleaved non-isolated converter for ultra-high step-up applications. This circuit utilises coupled inductor and voltage-lift techniques to achieve high voltage gain. In the proposed converter, the configuration of interleaved technique and winding-cross-coupled inductors not only reduces the input current ripple and current stress of semiconductor devices but also increases the voltage gain. Further, using voltage-lift technique helps to reach a very high voltage conversion ratio with low turn ratio and proper duty cycle. Since the voltage stress of semiconductor devices is low enough, low on resistance switches and low voltage ultra-fast recovery diodes are used. For this converter, high voltage gain, low conduction losses, low reverse recovery losses, high efficiency, low input current ripple, small volume and reduced cost are provided. Therefore, the proposed converter is a good choice for ultra-high step-up applications. The implemented 100 W laboratory prototype circuit with 18 V input voltage and unity turn ratio of coupled inductors reaches 360 V output voltage and 94.7% efficiency which validates the accuracy of theoretical analysis. 1 Introduction High step-up DC–DC converters are used in applications that the difference of output/input voltage level is large such as renewable energy systems, uninterrupted power supplies and so on. Due to large duty cycle problems and large voltage stress of semiconductor devices, conventional boost converter cannot achieve such high conversion ratio. Therefore, novel topologies are presented to increase voltage gain [1-3]. In applications that galvanic isolation between low and high voltage sides is not required, non-isolated converters are rather than isolated ones due to their simple topologies and control circuit. In these converters, coupled inductors are combined with other techniques to increase voltage gain [3-9]. One way to increase voltage gain is using voltage lift technique [3-6]. In [3], super-lift technique was used to increase the voltage gain. However, that converter suffers from inrush currents. In [5], super-lift technique was combined with coupled inductors. So, voltage gain was improved and inrush current problem was solved. Single-switch non-isolated converters suffer from pulsating input current caused by the coupled inductor [5, 6]. One way to solve this problem is using interleaved structure. By employing winding-cross-coupled inductors (WCCIs) in interleaved non-isolated converters, input current ripple and current stress of semiconductor devices are reduced and the voltage gain is increased [10-30]. In [19], an interleaved high step-up converter with coupled inductors was introduced. That converter was derived by integration of conventional coupled inductor boost converter and coupled inductor boost converter with passive snubber. That structure has provided a high voltage gain with a proper duty cycle and low turn ratio. However, there is large voltage spike across one of the switches. In [24], a high step-up interleaved converter with voltage multipliers and coupled inductors was presented. That converter uses large number of elements and its floating output limits its applications. An interleaved boost fly-back converter was presented in [21] which uses parallel input and series output to reduce input current ripple and increase voltage gain, but it needs high turn ratio of coupled inductors and high duty cycle to achieve ultra-high voltage gain. In [12], an interleaved converter using winding cross-coupled inductors and voltage multipliers was presented. However, it has floating output which is not suitable for some applications. In [22], a semi-interleaved converter was introduced. That converter has achieved high voltage gain using coupled inductors but it suffers from large input current ripples and high voltage spikes across its first switch. In [23], a diode-capacitor cell was used to improve the voltage gain. However, the large number of elements increases circuit volume and reduces efficiency. This paper introduces a novel interleaved non-isolated DC–DC converter for ultra-high step-up application. In this converter, super-lift technique and WCCIs are combined to increase conversion ratio and decrease voltage and current stress of semiconductor devices. So, low voltage low on-resistance switches can be employed which reduce conduction loss of switches and increase efficiency. In the other hand, the conduction losses of all diodes are reduced due to placing at low current side of the circuit and low forward voltage of low voltage ultra-fast recovery diodes. Further, the leakage inductance of coupled inductor helps to alleviate reverse recovery problem of all diodes and the utilised clamp circuit limits voltage spikes on the switches. In this converter, ultra-high conversion ratio is achievable by unity turn ratio and proper duty cycle. Low turn ratio of coupled inductors results in small core size, low cost and high efficiency. Since the interleaved structure is employed, current stress of power switches and input current ripple are decreased. Proposed converter is a good choice for ultra-high step-up applications such as fuel cells and photovoltaic systems. This paper is organised as follows. Section 2 introduces the proposed converter and presents steady-state analysis and performance comparison of the introduced converter. In Sections 3 and 4, design procedure of elements is explained and experimental results of a 100 W laboratory prototype circuit are discussed. At last, Section 5 gives the conclusion. 2 Proposed high step-up interleaved converter Fig. 1 shows schematic of the proposed converter. S1 and S2 are the power switches; Dc1 and Dc2 are the clamp diodes and Cc is the clamp capacitor shared with the two clamp circuits; D1–3 and C1–3 denote the diodes and capacitors of the lift circuit, respectively; Do and Co represent output diode and capacitor, respectively. Two coupled inductors are used. Each coupled inductor is modelled with a magnetising inductance Lm1/Lm2, a leakage inductance Lk1/Lk2 and an ideal transformer. The secondary winding of ideal transformer is represented by Ns and the primary winding is denoted by Np. The Ns/Np turn ratio is denoted by n. Fig. 1Open in figure viewerPowerPoint Schematic of the proposed interleaved converter In this converter, second windings of the coupled inductors are in series to raise the conversion ratio. Three diode capacitor circuits (D1–3, C1–3) are used to lift the output voltage three times. Second windings are placed in the capacitor charging/discharging loops of the lift circuits to increase voltage lift and prevent inrush current. Two passive clamp circuits are used which share their clamp capacitor Cc together. The clamp capacitor Cc is placed in series with C1 in the charging loop of C1 to increase its voltage. When S1 is on and S2 is off, D1 and D3 are conducting. So, C1 is charged through second windings of coupled inductors and Cc. Also, C3 is charged through C2 and second windings of coupled inductors. When S1 is off and S2 is on, D2 and Do are conducting. So, C2 is charged through second windings of coupled inductors and C1 and the input energy transfers to the output via coupled inductors. 2.1 Analysis of operating modes This converter works in continuous conduction mode (CCM) and duty cycles of power switches are more than 0.5 while they are identical. The gate signals of power switches are 180° phase shifted. To simplify the analysis, switches are assumed ideal. Also, Equivalent Series Resistance (ESR) of the inductors and capacitors and conduction voltage of diodes and switch are neglected. The magnetising inductors, Lm1 and Lm2, and capacitors are considered large enough to have constant current and constant voltage during a switching period. Coupling coefficient of coupled inductors are considered identical and represented by k, where k = k1 = k2. The operation of this converter is divided to ten operating modes in each switching period. Fig. 2 exhibits important key waveforms of the proposed converter. Figs. 3 and 4a demonstrate the equivalent circuits in each of these five operating modes. Mode I [t0, t1]: At t0 S1 is turned on, S2, D2 and Do are still in on state and other diodes are off as shown in Fig. 3a-left. The parasitic capacitor of S1 is discharged by the magnetising inductance and its voltage reaches to zero. So, the polarity of voltage across Lm1 is changed and its winding current is reduced. When it reaches to zero, the diodes turn off under zero current situation and this mode ends. Fig. 2Open in figure viewerPowerPoint Theoretical waveforms of the proposed interleaved converter Fig. 3Open in figure viewerPowerPoint Equivalent circuit of each operating mode(a) Left: mode I, right: mode II, (b) Left: mode III, right: mode IV, (c) Left: mode V, right: mode VI, (d) Left: mode VII, right: mode VIII Fig. 4Open in figure viewerPowerPoint Equivalent circuit of each operating mode(a) Mode IX, (b) Mode X Mode II [t1, t2]: In this mode, all diodes are off, both switches are in on state and the currents of both magnetising inductances are increasing linearly while they are storing energy. Simultaneously, the energy of output capacitor is transferred to the load. This mode ends when S2 is turned off. Fig. 3a-right demonstrates the equivalent circuit of this operating mode. Mode III [t2, t3]: S2 is turned off at t = t2 and its parasitic capacitor charges through the magnetising inductance. During this transient interval, iS2 reaches to zero in a short time and this mode ends (see Fig. 3b-left). Mode IV [t3, t4]: In this mode S2 is in off-state and Dc2, D1 and D3 turn on as demonstrated in Fig. 3b-right. The clamp capacitor charges through the leakage inductance and its current reduces. Meanwhile, the stored energy at the magnetising inductance Lm2 is transferred to C1 and C3 through Cc, secondary windings, S1 and diodes D1 and D3, respectively. When iDc reaches to zero, Dc2 turns off in zero current and this mode ends. Mode V [t4, t5]: In this mode, Dc2 turns off but other diodes and power switches keep their pervious situation as shown in Fig. 3c-left. So, releasing the stored energy of Lm2 through C1 and C3 is continued while Lm1 still stores energy. At t5, S2 is turned on and this mode ends. Mode VI [t5, t6]: At t0 S2 is turned on, S1, D1 and D3 are still in on state and other diodes are off as shown in Fig. 3c-right. The parasitic capacitor of S2 is discharged by the magnetising inductance and its voltage reaches to zero. So, the polarity of voltage across Lm2 is changed and its winding current is reduced. When it reaches to zero, the diodes turn off under zero current situation and this mode ends. Mode VII [t6, t7]: In this mode, all diodes are off, both switches are in on state and the currents of both magnetising inductances are increasing linearly while they are storing energy. Simultaneously, the energy of output capacitor is transferred to the load. This mode ends when S1 is turned off. Fig. 3d-left demonstrates the equivalent circuit of this operating mode. Mode VIII [t7, t8]: S1 is turned off at t = t7 and its parasitic capacitor charges through the magnetising inductance. During this transient interval, iS1 reaches to zero in a short time and this mode ends (see Fig. 3d-right). Mode IX [t8, t9]: In this mode S1 is in off-state and Dc1, D2 and Do turn on as demonstrated in Fig. 4a. The clamp capacitor charges through the leakage inductance and its current reduces. Meanwhile, the stored energy at the magnetising inductance Lm1 is transferred to C2 and Co through Cc, secondary windings, S2 and diodes D2 and Do, respectively. When iDc reaches to zero, Dc1 turns off in zero current and this mode ends. Mode X [t9, t10]: In this mode, Dc1 turns off but other diodes and power switches keep their pervious situation as shown in Fig. 4b. So, releasing the stored energy of Lm1 through C2 and Co is continued while Lm2 still stores energy. At t10, S1 is turned on and this mode ends. 2.2 Steady-state analysis This converter works at CCM. Here, the proposed converter is analysed at steady-state condition. For more simplifications, the short time intervals, i.e. modes I–III and VI–VIII are neglected here and just the large modes IV–V and IX–X are considered. During modes IV–V, S1 is conducting and S2 is in off state while during modes IX–X the power switches situations are reversed as shown in Fig. 3b-right, Fig. 3c-left and Fig. 4. In the following equations, the energy storing situation is denoted by index I and the energy releasing situation is represented by index II. During modes IV–V, as can be seen in Fig. 3b-right and Fig. 3c-left, Lm1 stores energy while Lm2 release the energy and this situation is reversed during modes IX–X. From Fig. 3b-right, Fig. 3c-left and Fig. 4 and volt-second balance, VCc, VLm1 and VLm2 can be derived by V L m 1 I = V L m 2 I = k ⋅ V in (1) V L m 1 II = V L m 2 II = − k D 1 − D ⋅ V in (2) V C c = 1 1 − D ⋅ V in (3) From Fig. 3b-right and Fig. 3c-left, the voltage across C1 and C3 can be obtained as V C 1 = V C c + n 1 V L m 1 I − n 2 V L m 2 II (4) V C 3 = V C c + V C 2 + n 1 V L m 1 I − n 2 V L m 2 II (5) On the other hand, from Fig. 4 VC2 and VCo can be achieved by V C 2 = V C c + V C 1 − n 1 V L m 1 II + n 2 V L m 2 I (6) V C o = V C c + V C 3 − n 1 V L m 1 II + n 2 V L m 2 I (7) From (1)–(7) and some simplifications, it yields V C 1 = 1 + k n 1 − k n 1 D − k n 2 D 1 − D V in (8) V C 2 = k n 1 + k n 2 + 2 1 − D V in (9) V C 3 = 2 k n 1 + k n 2 + 3 − k n 1 D − k n 2 D 1 − D V in (10) V C o = 2 k n 1 + 2 k n 2 + 4 1 − D V in (11) By considering n1 = n2 = n and neglecting leakage inductance, the voltage gain is V o = 4 n + 4 1 − D V in (12) Above equations help to find the voltage stress of semiconductor devices, which can be written as follows: V S 1 , 2 = V D c 1 , 2 = 1 1 − D ⋅ V in = 1 4 n + 4 ⋅ V o (13) V D 1 = V D o = 2 n + 1 1 − D ⋅ V in = 2 n + 1 4 n + 4 ⋅ V o (14) V D 2 = V D 3 = 2 n + 2 1 − D ⋅ V in = 1 2 ⋅ V o (15) Ampere-second balance for capacitors in one switching period shows that the average current of all diodes and the output current are identical I D 1 − 3 , avr = I D c 1 − 2 , avr = I D o , avr = I o = 1 − D 4 n + 4 I in (16) In this converter, C1 charges through NS1 and NS2. So, the average current ratio of Lm1 and Lm2 can be calculated as follows: I L m 2 I L m 1 = V N s 1 V N s 2 = 1 − D D (17) So, it yields I L m 1 = D I in , I L m 2 = ( 1 − D ) I in (18) From Fig. 1 and (18), average current stress of the switches can be written as follows: I S 1 = I L m 1 = D I i n , I S 2 = I L m 2 = ( 1 − D ) I in (19) 2.3 Design procedure of components Proposed converter is designed in 100 W output power and 100 kHz switching frequency. With a proper duty cycle (D≃0.6) and unity turn ratio, this circuit converts 18 V input voltage to 360 V output voltage. The magnetising inductor current ripple can be written as follows: Δ i L m = D V in L m f (20) In order to assure CCM operation, the following equation should be provided: I L m 1 = D I in > Δ i L m 2 , I L m 2 = ( 1 − D ) I in > Δ i L m 2 (21) From (12), (20)–(21) and some simplifications, the following equations should be provided to assure CCM operation: L m 1 ≥ 1 − D 2 R l BCM 2 4 n + 4 2 f (22) L m 2 ≥ D 1 − D R l BCM 2 4 n + 4 2 f (23) where Rl(BCM) denotes the boundary condition load and it is assumed 20% of rated power. So, in order to provide above equations Lm1 and Lm2 are considered 150 µH. According to the voltage ripple equation of capacitor given in (24), the capacitor values can be calculated from (25) and (26) C ⋅ Δ V C = I C ⋅ Δ t (24) C 1 − 3 = C c = I o Δ V C ⋅ f s (25) C o = D ⋅ I o Δ V C ⋅ f s (26) where ΔVC is capacitor voltage variations, which is assumed 0.2 and 1–2% of the average voltage, for output capacitor and the others, respectively. According to the ESR effect and above equations and in order to have equal diode current stress, all capacitors are chosen equal and with the value of 4.7 µF. From (13) and circuit prototype specifications mentioned before, the voltage stress of power switches computed about 45 V. Therefore, it is possible to employ low on-resistance power MOSFETs. According to (14)–(16), voltage stress of all diodes are lower than 200 V while their average current is lower than 0.3 A. So, BYV28-200 is selected which is a very fast recovery diode. 2.4 Efficiency analysis Power losses of the proposed converter consist of conduction, switching and parasitic capacitive losses of the switches, diode conduction losses, capacitor losses, copper losses and core losses. Since the capacitors are mostly selected from low resistance polyester family, their losses are neglected here. Conduction losses of switches Ploss−sw(conduction) can be computed from following equation: P loss − sw conduction = R d s × f sw × ∫ T i S 2 (27) where Rds and fsw introduce the switches turn on resistance and switching frequency, respectively. Parasitic capacitive turn on losses of the switches Ploss−Cout are P loss − C out = 1 2 × C out × V d s 2 × f sw (28) where Cout and Vds introduce drain-source parasitic capacitor and drain-source voltage of the switches, respectively. The switching losses of the switches are written as follows: P loss − sw switching = 1 2 × I 0 × V d s × t on + t off × f sw (29) where I0 is the switch current when switch turns off. The diode conduction losses can be computed as follows: P loss − D conduction = I D , ave × V F (30) where Iave−D and VF introduce average current of diodes and forward voltage of diodes, respectively. The copper losses can be written as follows: P loss − Rw = R w × I rms − Rw 2 (31) where Rw introduce winding resistance and Irms−Rw is inductor rms current. So, the output power losses is P loss − o = P loss − sw conduction + P loss − C out + P loss − sw switching + P loss − D conduction + P loss − R w + P loss − core (32) where Ploss−core is the core loss which is derived from core datasheet. 3 Performance comparison The amount of the variables depends on the n, D and other parameters. However, since D is less than one and is preferred to be selected near 0.5 in order to reduce switch conduction losses and input current ripple, also unity turn ratio n = 1 is preferred to reduce leakage inductance value, the proposed converter is among the best voltage gains. Operation of the proposed converter and recent high step-up interleaved non-isolated converters are compared in Table 1 in terms of voltage gain, voltage stress of switches and output diode, current stress of switches and diodes, number of elements, clamp circuit and input–output ground connection. Fig. 5a demonstrates voltage gain of the proposed converter versus duty cycle for various coupling coefficients. The terms of voltage gain, voltage stress of switches and voltage stress of output diode, respectively, are compared with recent papers in Figs. 5b–d versus turn ratio at D≃0.6. As can be seen, proposed converter obtains higher or equal conversion ratio and lower or equal switch voltage stress for all turn ratios in comparison with other converters. Also, the proposed converter has lower output diode voltage stress than [10-12] for all turn ratios. Table 1. Comparison of the proposed converter with previous interleaved converters [10] [11] [12] [21] [23] Proposed converter voltage gain 4 n + 4 1 − D 2 n + 2 1 − D 2 n + 4 1 − D 3 n D + 1 1 − D 2 n + 6 1 − D 4 n + 4 1 − D voltage stress of switch V o 4 n + 4 V o 2 n + 2 V o 2 n + 4 V o n D + 1 V o 2 n + 6 V o 4 n + 4 voltage stress of output diode V o 2 2 n + 1 V o 2 n + 2 2 n + 1 V o 2 n + 4 V o n D + 1 n ⋅ V o 2 n + 6 2 n + 1 V o 4 n + 4 maximum average current stress of diodes 1 − D I in 4 n + 4 — — — 1 − D I in n 1 − D I in 4 n + 4 maximum average current stress of switches I in 2 I in 2 I in 2 I in 3 I in 2 D ⋅ I in number of switches 2 2 2 3 2 2 number of diodes 4 4 4 6 10 6 number of capacitor 4 5 4 4 10 5 clamp circuit no yes yes yes yes yes grounded output no yes no yes yes yes Fig. 5Open in figure viewerPowerPoint Comparative graphics(a) Voltage gain of the proposed convertor versus duty cycle for various coupling coefficient k = Lm/(Lm + Lk), (b) Voltage gain versus turn ratio, (c) Voltage stress of the switches versus turn ratio normalised by Vo, (d) Voltage stress of output diode versus turn ratio normalised by Vo The proposed converter can attain an ultra-high conversion ratio with low duty cycle and turn ratio and reduced voltage stress. Therefore, conduction loss and coupled inductor loss are reduced and the efficiency is improved. 4 Experimental results The laboratory prototype circuit of the proposed converter is implemented and tested at Po = 100 W which converts 18–360 V. This conversion ratio is realised by unity turn ratio and proper duty cycle (D≃0.6). The specifications of the laboratory prototype are given in Table 2. Table 2. Specifications of the laboratory prototype circuit Symbol Parameter Value Vin input DC voltage 18 V Vout output DC voltage 360 V Po maximum output power 100 W fs switching frequency 100 kHz Cc, C1–3, Co capacitors 4.7 µF Dc1–2, D1–3, Do diodes BYV28-200 S1, S2 power switch IRFB4110 n1, n2 turn ratio 1 Lm1, Lm2 magnetising inductance 150 µH Lk1, Lk2 leakage inductance 3 µH — magnetising core EI33/29 — wire 0.5106 mm -litz × 3 — primary/secondary winding turns 30/30 The photograph of implemented circuit is shown in Fig. 6. Fig. 6Open in figure viewerPowerPoint Photograph of the laboratory prototype Fig. 7 demonstrates voltage and current waveforms of power switches and clamp capacitors. As can be seen, the obtained voltage stress is matched to (13). The voltage and current waveforms of other diodes are given in Fig. 8. This figure shows that the voltage waveforms verify (14) and (15). The voltages of capacitors, input and output voltages, coupled inductor currents iLk1, iLk2 and input current are shown in Figs. 9 and 10. As can be seen, the voltages of capacitors have low voltage ripple and input current ripple is reduced. Also, the high voltage gain of (12) is realised. Fig. 7Open in figure viewerPowerPoint Experimental results: voltage and current waveforms of(a) Switch S1, (b) Switch S2, (c) Clamp diode DC1, (d) Clamp diode DC2. Time scale is 5 µs/div Fig. 8Open in figure viewerPowerPoint Experimental results: voltage and current waveforms of(a) Diode D1, (b) Diode D2, (c) Diode D3, (d) Output diode DO. Time scale is 5 µs/div Fig. 9Open in figure viewerPowerPoint Experimental results: the waveforms of(a) Capacitor voltages VC1, VC3, (b) Capacitor voltage VC2, (c) Input and output voltages Vin, Vout, (d) Inductor currents iLk1, iLk2, (e) Input current iin. Time scale is 5 µs/div Fig. 10Open in figure viewerPowerPoint Waveforms of input current iin. Time scale is 5 µs/div The proposed converter achieves high voltage gain with unity turn ratio and proper duty cycle which increases the efficiency. In Fig. 11, the efficiency curve of the proposed converter is compared with [10-12, 21, 23] at different loads. For this comparison, same components are used for all circuits except the switches. Due to high voltage spikes appear on the switches of [10] and larger voltage stress of the switches in [11, 21], IRFP4668 is used for them while IRFB4110 is used in the proposed converter [11, 23]. As can be observed, the efficiency of the proposed converter is increased in comparison with the most of papers. The maximum efficiency yields 96.7% at Po = 25 kHz and full load efficiency is obtained 94.7%. Fig. 11Open in figure viewerPowerPoint Efficiency curve of the proposed converter and recent papers at different loads Table 3 and Fig. 12 demonstrate the power loss distribution of the proposed interleaved converter at full load condition. Since most of capacitors are from low ESR polyester family, in this analysis the capacitor losses are ignored. Also, PCB track loss is neglected. From Table 3, the theoretical efficiency is obtained 95% while the measured efficiency is 94.7%. Table 3. Power loss distribution of the proposed interleaved converter at full load switches Vds(max), Isw,rms S1 45 V, 3.8 A diodes VF, ID,ave D1–3, Do 1.1 V, 0.3 A S2 45 V, 2.6 A Dc1 1.1 V, 0.2 A Dc2 1.1 V, 0.1 A S1 capacitive turn on loss (W) 0.068 W S2 capacitive turn on loss 0.068 W S1 switching loss 0.85 W S2 switching loss 0.58 W S1 conduction loss 0.067 W S2 conduction loss 0.033 W Dc1 conduction loss 0.22 W D1–3, Do, conduction loss 4*0.33 W Dc2 conduction loss 0.11 W copper loss total inductor loss 0.87 W 1.95 W core loss 1.08 W total loss total theoretical loss 5.26 W total experimental loss 5.6 W theoretical efficiency 95% experimental efficiency 94.7% Fig. 12Open in figure viewerPowerPoint Pie graph of power loss distribution of the proposed converter The theoretical values, simulated values and experimental values of output voltage, voltage stress of switches and diodes and full load efficiency are tabulated in Table 4. As can be seen, the experimental results confirm the theoretical and simulated results. The difference between simulated and experimental efficiency values is because of ignoring core losses in simulated efficiency. Also, the difference of theoretical and experimental efficiency values is because of neglecting capacitors and PCB track losses in theoretical efficiency. Table 4. Specifications of the laboratory prototype circuit Theoretical Simulated (ORCAD PSPICE) Experimental output voltage 360 V 375 V 360 V voltage stress of switches 45 V 47 V 48 V voltage stress of D1, Do 135 V 137 V 140 V voltage stress of D2, D3 180 V 183 V 185 V full load efficiency 95% 96% 94.7% 5 Conclusion An interleaved high step-up converter by utilising coupled inductors and voltage lift circuit has been presented for ultra-high step-up usage. A very high conversion ratio is achieved with unity turn ratio and proper duty cycle. The voltage and current stress on semiconductor devices are low enough to use low voltage low resistance switches and very fast low voltage diodes. Therefore, conduction loss is reduced and reverse recovery problem is alleviated. Further, because of interleaved structure of the proposed converter, pulsating current problem in coupled inductor based circuits is solved. The features of the proposed converter are: high voltage gain, low voltage stress, low conduction losses, low reverse recovery losses, high efficiency, low input current ripple and small volume. The prototype circuit is implemented and tested at 100 W, which validates the theoretical analysis. 6 References 1Abutbul, O., Gherlitz, A., Berkovich, Y., et al.: ‘Step-up switching-mode converter with high voltage gain using a switched-capacitor circuit’, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 2003, 50, (8), pp. 1098– 1102 2Qun, Z., Lee, F.C.: ‘High-efficiency, high step-up DC-DC converters’, IEEE Trans. Power Electron., 2003, 18, (1), pp. 65– 73 3Luo, F.L., Ye, H.: ‘Positive output super-lift converters’, IEEE Trans. Power Electron., 2003, 18, (1), pp. 105– 113 4Mohammadzadeh Shahir, F., Babaei, E., Farsadi, M.: ‘Voltage-lift technique based nonisolated boost DC–DC converter: analysis and design’, IEEE Trans. Power Electron., 2018, 33, (7), pp. 5917– 5926 5Fani, R., Farshidi, E., Adib, E., et al.: ‘Analysis and implementation of high step-up DC/DC convertor with modified super-lift technique’, J. Power Electron., 2019, 19, (3), pp. 645– 654 6Fani, R., Farshidi, E., Adib, E., et al.: ‘Analysis, design and implementation of a ZVT high step up DC/DC converter with continuous input current’, IEEE Trans. Ind. Electron., 2020, 67, (12), pp. 10455– 10463, doi: 10.1109/TIE.2019.2960727 7Liu, H., Hu, H., Wu, H., et al.: ‘Overview of high-step-up coupled-inductor boost converters’, IEEE J. Emerging Sel. Topics Power Electron., 2016, 4, (2), pp. 689– 704 8Forouzesh, M., Shen, M., Yari, K., et al.: ‘High-efficiency high step-up DC–DC converter with dual coupled inductors for grid-connected photovoltaic systems’, IEEE Trans. Power Electron., 2017, 33, (7), pp. 5967– 5982 9Premkumar, M., Subramaniam, U., Haes Alhelou, H., et al.: ‘Design and development of non-isolated modified SEPIC DC-DC converter topology for high-step-up applications: investigation and hardware implementation’, Energies, 2020, 13, (15), p. 3960, doi: 10.3390/en13153960 10Chen, Y.T., Lu, Z.X., Liang, R.H.: ‘Analysis and design of a novel high-step-up DC/DC converter with coupled inductors’, IEEE Trans. Power Electron., 2017, 33, (1), pp. 425– 436 11He, L., Liao, Y.: ‘An advanced current-autobalance high step-up converter with a multicoupled inductor and voltage multiplier for a renewable power generation system’, IEEE Trans. Power Electron., 2016, 31, (10), pp. 6992– 7005 12Fekri, M., Molavi, N., Adib, E., et al.: ‘High voltage gain interleaved DC–DC converter with minimum current ripple’, IET Power Electron., 2017, 10, (14), pp. 1924– 1931 13Moradi Sizkoohi, H., Milimonfared, J., Taheri, M., et al.: ‘High step-up soft-switched dual-boost coupled-inductor-based converter integrating multipurpose coupled inductors with capacitor-diode stages’, IET Power Electron., 2015, 8, (9), pp. 1786– 1797 14Akhlaghi, B., Molavi, N., Fekri, M., et al.: ‘High step-up interleaved ZVT converter with low voltage stress and automatic current sharing’, IEEE Trans. Ind. Electron., 2017, 65, (1), pp. 291– 299 15Shaneh, M., Niroomand, M., Adib, E.: ‘Ultra high-step up non-isolated interleaved boost converter’, IEEE J. Emerging Sel. Topics Power Electron., 2020, 8, (3), pp. 2747– 2758, doi: 10.1109/JESTPE.2018.2884960 16Packnezhad, M., Farzanehfard, H., Adib, E.: ‘Integrated soft switching cell and clamp circuit for interleaved high-step-up converters’, IET Power Electron., 2019, 12, (3), pp. 430– 437 17Li, W., Zhao, Y., Deng, Y., et al.: ‘Interleaved converter with voltage multiplier cell for high step-up and high-efficiency conversion’, IEEE Trans. Power Electron., 2010, 25, (9), pp. 2397– 2408 18Tseng, K., Huang, C.: ‘High step-up high-efficiency interleaved converter with voltage multiplier module for renewable energy system’, IEEE Trans. Ind. Electron., 2014, 61, (3), pp. 1311– 1319 19Zheng, Y., Xie, W., Smedley, K.M.: ‘Interleaved high step-up converter with coupled inductors’, IEEE Trans. Power Electron., 2019, 34, (7), pp. 6478– 6488 20Dwari, S., Parsa, L.: ‘An efficient high-step-up interleaved DC–DC converter with a common active clamp’, IEEE Trans. Power Electron., 2011, 26, (1), pp. 66– 78 21Brockveld, S.L., Waltrich, G.: ‘Boost–flyback converter with interleaved input current and output voltage series connection’, IET Power Electron., 2018, 11, (8), pp. 1463– 1471 22Majarshin, A.R., Babaei, E.: ‘High step-up DC–DC converter with reduced voltage and current stress of elements’, IET Power Electron., 2019, 12, (11), pp. 2884– 2894 23Revathi, B.S., Mahalingam, P.: ‘Non-isolated high gain DC–DC converter with low device stress and input current ripple’, IET Power Electron., 2018, 11, (15), pp. 2553– 2562 24Alghaythi, M.L., O'Connell, R.M., Islam, N.E., et al.: ‘A high step-up interleaved DC-DC converter with voltage multiplier and coupled inductors for renewable energy systems’, IEEE Access, 2020, 8, pp. 123165– 123174, doi: 10.1109/ACCESS.2020.3007137 25Tseng, K., Cheng, C., Chen, C.: ‘High step-up interleaved boost converter for distributed generation using renewable and alternative power sources’, IEEE J. Emerging Sel. Topics Power Electron., 2017, 5, (2), pp. 713– 722 26Nouri, T., Vosoughi, N., Hosseini, S.H., et al.: ‘An interleaved high step-up converter with coupled inductor and built-in transformer voltage multiplier cell techniques’, IEEE Trans. Ind. Electron., 2019, 66, (3), pp. 1894– 1905 27Salehi, S.M., Dehghan, S.M., Hasanzadeh, S.: ‘Interleaved-input series-output ultra-high voltage gain DC–DC converter’, IEEE Trans. Power Electron., 2019, 34, (4), pp. 3397– 3406 28Chen, S., Yang, S., Huang, C., et al.: ‘High step-up interleaved converter with three-winding coupled inductors and voltage multiplier cells’. IEEE Proc. Int. Conf. Industrial Technology (ICIT), Melbourne, Australia, 2019, pp. 458– 463 29Liu, X., Zhang, X., Hu, X., et al.: ‘Interleaved high step-up converter with coupled inductor and voltage multiplier for renewable energy system’, CPSS Trans. Power Electron. Appl., 2019, 4, (4), pp. 299– 309 30Alghaythi, M.L., O'Connell, R.M., Islam, N.E., et al.: ‘A high step-up interleaved DC-DC converter with voltage multiplier and coupled inductors for renewable energy systems’, IEEE Access, 2020, 8, pp. 123165– 123174, doi: 10.1109/ACCESS.2020.3007137 Citing Literature Volume13, Issue18December 2020Pages 4261-4269 FiguresReferencesRelatedInformation
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