Portal de Periódicos da CAPES

Laser Chemical Etching Trench Refinements for Backside Debug Journey to the Circuit Layer

2020; Volume: 83348; Linguagem: Inglês

10.31399/asm.cp.istfa2020p0357

0890-1740

Matthew M. Mulholland, Shida Tan, Muhammad Usman Raza, Matthew Levesque, Jordan Furlong, Christopher Ferri, Robert Chivas, Michael DiBattista, Scott Silverman,

Semiconductor materials and devices

Abstract The journey to the circuit layer will be described by first discussing baseline processes of laser assisted chemical etching (LACE) steps before the focused ion beam (FIB) workflow. These LACE processes take advantage of a dual 532 nm continuous wave (CW) and pulse laser system, however limitations and overhead that is transferred over to the FIB operator will be demonstrated. Experiments show an additional third 355 nm ultraviolet (UV) pulse laser process introduction into the workflow can further reduce the remaining silicon thickness (RST) relieving FIB overhead. In addition, complex pulse laser patterning techniques will show a refinement to nonuniform produced silicon. Finally, other pulse laser patterning techniques such as polygon etch capability will allow laser etching around and in-between features to enhance circuit layer accessibility for debug operations.