Generalized diamond‐type single DC‐source switched‐capacitor based multilevel inverter with step‐up and natural voltage balancing capabilities
2021; Institution of Engineering and Technology; Volume: 14; Issue: 6 Linguagem: Inglês
10.1049/pel2.12111
ISSN1755-4543
AutoresSaeid Deliri, Kazem Varesi, Yam P. Siwakoti, Frede Blaabjerg,
Tópico(s)Advanced DC-DC Converters
ResumoIET Power ElectronicsVolume 14, Issue 6 p. 1208-1218 ORIGINAL RESEARCH PAPEROpen Access Generalized diamond-type single DC-source switched-capacitor based multilevel inverter with step-up and natural voltage balancing capabilities Saeid Deliri, Power Electronics Research Lab. (PERL), Faculty of Electrical Engineering, Sahand University of Technology, Tabriz, IranSearch for more papers by this authorKazem Varesi, Corresponding Author k.varesi@sut.ac.ir orcid.org/0000-0002-9802-1058 Power Electronics Research Lab. (PERL), Faculty of Electrical Engineering, Sahand University of Technology, Tabriz, Iran Correspondence Kazem Varesi, Power Electronics Research Lab. (PERL), Faculty of Electrical Engineering, Sahand University of Technology, Tabriz, Iran, PO. BOX 51335/1996. Email: k.varesi@sut.ac.irSearch for more papers by this authorYam P. Siwakoti, Faculty of Engineering and IT, University of Technology Sydney, Ultimo, AustraliaSearch for more papers by this authorFrede Blaabjerg, orcid.org/0000-0001-8311-7412 Faculty of Engineering and Science, Department of Energy Technology, Aalborg University, Aalborg, DenmarkSearch for more papers by this author Saeid Deliri, Power Electronics Research Lab. (PERL), Faculty of Electrical Engineering, Sahand University of Technology, Tabriz, IranSearch for more papers by this authorKazem Varesi, Corresponding Author k.varesi@sut.ac.ir orcid.org/0000-0002-9802-1058 Power Electronics Research Lab. (PERL), Faculty of Electrical Engineering, Sahand University of Technology, Tabriz, Iran Correspondence Kazem Varesi, Power Electronics Research Lab. (PERL), Faculty of Electrical Engineering, Sahand University of Technology, Tabriz, Iran, PO. BOX 51335/1996. Email: k.varesi@sut.ac.irSearch for more papers by this authorYam P. Siwakoti, Faculty of Engineering and IT, University of Technology Sydney, Ultimo, AustraliaSearch for more papers by this authorFrede Blaabjerg, orcid.org/0000-0001-8311-7412 Faculty of Engineering and Science, Department of Energy Technology, Aalborg University, Aalborg, DenmarkSearch for more papers by this author First published: 22 March 2021 https://doi.org/10.1049/pel2.12111AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinked InRedditWechat Abstract This paper proposes a diamond-shaped high step-up switched-capacitor based basic multilevel inverter topology. The basic switched-capacitor (SC) stage consists of 2 active switches, 2 diodes, and 2 capacitors. Using a single DC source with the unfolding circuit (10 switches, 5 capacitors, and 5 diodes) results in the production of 17 voltage-steps at the output with the gain of up to 8 times of the input voltage. By extending the diamond-shaped switched-capacitor stages, higher voltage levels and voltage gains can be possible. The suggested topology employs two half-bridges (instead of a full-bridge) to produce positive, zero, and negative steps, which reduces the Voltage Stress (VS) on two output switches and consequently reduces Total Voltage Stress (TVS). In addition, the natural voltage balancing of capacitors eliminates the need to an additional control circuitry and consequently reduces the total converter size, complexity, and cost. In addition, modularity, scalability, low voltage ripple on capacitors, low total voltage stress, high power quality, and capability of supplying low/medium power factor (R-L) loads are some of the merits of the proposed topology. The low Cost Function (CF) obtained in the comparison section as well as experimental results verifies the advantages of the proposed topology. 1 INTRODUCTION In recent years, multilevel inverters have gained tremendous attention among power electronic converters due to their outstanding features such as: simple structure, suitability for medium/high voltage/power applications, low electromagnetic interference, low total harmonic distortion (THD), and improved power quality [1-3]. The DC supplies as well as switches and diodes are included devices of multilevel inverters. But numerous devices are demanded for reaching increased steps. In literature, many structures have been presented profiting from the reduced number of devices [4-6]. The reduction in semiconductor device count leads to reduced gate-driver circuits and reduced overall size and cost [7]. Usually, the DC sources are bulkier, heavier, and more expensive than other parts in multilevel inverters. So, most of the papers have focused on presenting structures with less number of DC supplies [8]. The capacitors are good candidates for replacing DC sources, which results in the introduction of capacitor-based multilevel inverters (or called “Switched-Capacitor Based Multi-Level Inverters (SCBMLIs)”) [9-24]. In SCBMLIs, DC source(s) and pre-charged capacitor(s) are synthesized to produce staircase voltage waveform. In [9-11], the application of capacitors has only decreased the number of sources (unity gain). But in [12-24], the enhanced gain has also been reported besides reduced source count. The charge balancing of capacitors is the main challenge of SCBMLIs [25]. The topology presented in [26] requires additional auxiliary control circuits for charge balancing of the capacitor, which increases the total cost and size of the converter. But, in [9-24], the charge balancing of capacitors is done naturally (without auxiliary circuits) leading to less complexity and simple control. The topologies presented in [9, 11, 13–19, 21, 23, 24, 27] are modular and can be extended by increment of switched-capacitor stages, where the non-modular structures presented in [10, 12, 20, 22] can only be extended by cascading the basic units. This increases the number of sources/devices, weight, cost, and volume of the converter. The extension of [14–19, 23, 24, 27] increases the number of steps and voltage gain, but in [9–13, 20, 22] the voltage gain remains constant. The SCBMLIs presented in [9, 28–30] employ an H-bridge unit to provide negative steps, which imposes maximum voltage stress ( = Vo,max) and consequently high losses on H-bridge switches. To overcome this shortcoming, two half-bridges [11–15, 22–24, 27] or a developed H-bridge [10, 16–19] can be applied (instead of H-bridge) to create negative steps, where only two switches (instead of 4 switches) are imposed to maximum voltage stress. The creation of AC voltage waveform can be free of H-bridge, developed H-bridge or half-bridges. For example, the bipolar output voltage waveform generation of [21] is accomplished inherently, which reduces the total voltage stress. The SCBMLIs presented in [19-24] have been investigated in detail, in the comparison section. Another important feature in SCBMLIs is the quality of output voltage waveform. Higher number of steps leads to higher quality and lower THDs. However, this objective can be obtained in expense of increased devices, cost, weight, and volume. So, there should be a trade-off between number of devices (cost) and number of steps. While the cost factor is dominant, a linear relationship is preferred between number of levels and devices [20-24]. But if quality factor is the main objective, an exponential relation between number of steps and devices is aimed [19], where large number of steps and accordingly high quality and low THD can be achieved. This paper suggests a modular developed diamond-type single-source SCBMLI configuration that benefits from increased levels per device. Application of 2 half-bridges (for creating negative steps) has reduced the total voltage stress. The suggested topology is extended by adding switched-capacitor stages to reach more steps and higher voltage gains. Also, the suggested structure can properly supply the R-L loads. In Sections 2 and 3, the proposed basic and generalized topologies have been introduced. Then, the modulation technique as well as losses analysis and design procedure of capacitors have been explained in Sections 4 and 5. The comparative analysis is also presented in Section 6. The experimental results and conclusions have been presented in Sections 7 and 8, respectively. 2 PROPOSED DEVELOPED 17-LEVEL TOPOLOGY The proposed 17-level configuration (shown in Figure 1) is consisted of a single DC-source, 10 switches, 5 capacitors, and 5 diodes. All the switches are unidirectional. So, the count of switches (NSwitch), MOSFETs (NMOSFET), and gate-driver circuits (NDriver) are the same. Thus, N S o u r c e = 1 , N S w i t c h = N M O S F E T = N D r i v e r = 10 N C a p a c i t o r = 5 , N D i o d e = 5 , N D e v i c e = 31 (1) FIGURE 1Open in figure viewerPowerPoint Proposed 17-level inverter topology Table 1 describes the switching states and charge/discharge process of capacitors in the proposed configuration. Due to the symmetric characteristic of the proposed structure, the H1, H2, and S1-S3 are switched in complementary manner with H3, H4, and P1-P3, respectively. TABLE 1. Switching pattern and charge/discharge process of capacitors in proposed 17-level topology Vo S1S2S3P1P2P3H1H2H3H4 D1D2D3D4D5 C1C2C3C4C5 +8VIN 1000110110 01010 ↓↑↓↑↓ +7VIN 0001110110 10010 ↑↓↓↑↓ +6VIN 1100010110 00110 ↓↓↑↑↓ +5VIN 0101010011 10010 ↑↓↓↑↓ +4VIN 1010100110 01001 ↓↑↓→↑ +3VIN 0011100110 10001 ↑↓↓→↑ +2VIN 1110000110 00101 ↓↓↑→↑ +1VIN 0111000011 10001 ↑↓↓→↑ 0 (Io > 0) 1110000011 00101 ↓↓↑→↑ 0 (Io < 0) 1000111100 01010 ↓↑↓↑→ −1VIN 0001111100 10010 ↑↓↓↑→ −2VIN 1000111001 01010 ↓↑↓↑→ −3VIN 0101011001 10010 ↑↓↓↑→ −4VIN 1100011001 00110 ↓↓↑↑→ −5VIN 0011101100 10001 ↑↓↓↓↑ −6VIN 1010101001 01001 ↓↑↓↓↑ −7VIN 0111001001 10001 ↑↓↓↓↑ −8VIN 1110001001 00101 ↓↓↑↓↑ Figure 2 displays the charging path of C1-C5 capacitors of proposed topology. As seen in Figure 2, the C1 is charged by input voltage source, through P1 and D1. This process happens in 8 modes of each cycle, during the generation of ±VIN, ±3VIN, ±5VIN and ±7VIN voltage levels. This guarantees the voltage balancing of C1 to VIN (VC1 = VIN). The C2 capacitor is paralleled with series connection of VIN and C1, through S1, P2 and D2. So, the C2 is charged to VC2 = VIN +VC1 = 2VIN. The charging of C2 occurs during 5 intervals at each cycle, while generation of zero (Io < 0), +4VIN, +8VIN, −2VIN and −6VIN voltage levels (Table 1). Similarly, the C3 is paralleled with series connection of VIN and C1, through S1, S2 and D3. Accordingly, the C3 is charged to VC3 = VIN + VC1 = 2VIN. The charging of C3 occurs in 5 intervals at each cycle, while generation of zero (Io ≥ 0), +2VIN, +6VIN, −4VIN and −8VIN output voltage levels (Table 1). Based on Figure 2, the C4 is paralleled with series connection of VIN, C1 and C2, through S1, S2, P3, D3 and D4. So, the C4 is charged to VC4 = VIN + VC1 + VC2 = 4VIN. The process takes place during 9 modes (at zero (Io < 0), +5VIN, +6VIN, +7VIN, +8VIN, −1VIN, −2VIN, −3VIN and −4VIN voltage levels) at each switching cycle. Similarly, the C5 is paralleled with series connection of VIN, C1 and C2, through S1, S2, S3, D3 and D5. So, it is charged to VC5 = VIN + VC1 + VC2 = 4VIN. The charging process of C5 happens in 9 operational modes (while generation of zero (Io ≥ 0), +1VIN, +2VIN, +3VIN, +4VIN, −5VIN, −6VIN, −7VIN and −8VIN voltage levels). Due to numerous charging modes of C1-C5 capacitors, the voltage of capacitors is naturally balanced on desired values presented in Equation (2), during initial cycles. Then, the proposed topology reaches to its steady-state operation. V C 1 = V I N , V C 2 = V C 3 = 2 V I N , V C 4 = V C 5 = 4 V I N (2) FIGURE 2Open in figure viewerPowerPoint The charging path of C1–C5 capacitors Figure 3 shows equivalent circuits of the proposed converter during the generation of different voltage steps. It is evident from Figure 3 that the proposed topology can simultaneously produce the output voltage level and balance the charge of capacitors at desired values, which is called “natural voltage balancing”. FIGURE 3Open in figure viewerPowerPoint Operational modes of proposed 17-level converter The voltage stress and Normalized Voltage Stress (NVS) on semiconductors are shown in Table 2. Note that the NVS is defined as voltage stress on semiconductor divided by maximum output voltage: NVS = (VS/Vo,max). The suggested basic topology applies two half-bridges instead of a full-bridge, which keeps the switch count the same, but decreases the voltage stress on H2 and H4 switches to quarter. Accordingly, the losses and expense of H2, H4 as well as total voltage stress of the converter are reduced. Only H1, and H3 withstand Vo,max. As seen from Equation (3), the Normalized Total Voltage Stress (NTVS) of proposed topology is an acceptable amount of 5.875. The NTVS is equal to the sum of semiconductors' voltage stress divided by peak output voltage, as in Equation (3). N T V S = ∑ i = 1 3 V S S i + ∑ i = 1 3 V S P i + ∑ i = 1 5 V S D i + ∑ i = 1 4 V S H i V o , max = 47 V I N 8 V I N = 5.875 (3) TABLE 2. Voltage stress (VS) on switches/diodes of proposed 17-level topology Switch VS NVS [%] Switch VS NVS [%] Diode VS NVS [%] S1 VIN 12.5 P1 VIN 12.5 D1 VIN 12.5 S2 2VIN 25 P2 2VIN 25 D2 2VIN 25 S3 4VIN 50 P3 4VIN 50 D3 2VIN 25 H1 8VIN 100 H3 8VIN 100 D4 4VIN 50 H2 2VIN 25 H4 2VIN 25 D5 4VIN 50 3 PROPOSED GENERALIZED TOPOLOGY The proposed basic topology can be extended by increasing switched-capacitor stages to obtain more voltage gains and output steps, as shown in Figure 4. Each switched-capacitor stage contains 2 unidirectional switches (MOSFETs), 2 capacitors, and 2 diodes. The addition of each switched-capacitor stage doubles positive and negative steps, which improves the output voltage quality and reduces the THD of the suggested topology. Then, the filter can be eliminated or downsized. Also, the voltage gain is doubled by increment of each switched-capacitor stage. FIGURE 4Open in figure viewerPowerPoint Proposed extended topology The number of steps and devices, as well as gain of generalized configuration, have been summarized in Table 3, where ‘n’ denotes the number of switched-capacitor stages. TABLE 3. Description of proposed generalized topology Parameter Value Parameter Value NLevel 2(n+2)+1 NCapacitor 2n+1 NSwitch = NMOSFET 2n+6 NDiode 2n+1 NDriver 2n+6 NDevice 8n+15 NSource 1 Gain 2(n+1) 4 SWITCHING TECHNIQUE In this study, the “Nearest Level” (or named as “fundamental frequency”) technique has been employed as modulation strategy. In this technique, a sinusoidal waveform with fundamental frequency of 50 Hz is considered as the reference waveform (VRef = Vmsin(ωt)). The magnitude of reference waveform can be selected through 0 ≤ Vm ≤ NP = (NLevel − 1)/2, where NP denotes the total number of positive levels. To guarantee maximum number of levels, the Vm should be selected as close as possible to NP. In proposed 17-level topology, the NP is equal to 8. Therefore, the reference waveform is defined as in Equation (4): V R e f = 8 sin ( 2 π × 50 t ) = 8 sin ( 100 π t ) (4) In nearest level modulation technique, the reference waveform is compared with producible voltage levels (0, ±VIN, ±2VIN,..., ±8VIN). At each instant (t), the difference between producible voltage levels and reference waveform (called “error”) is monitored. The nearest level to the reference waveform is specified by checking relevant error values. The level that has an error less than 0.5 is the nearest one to the reference waveform. So, it is produced at the output port. While the difference between reference waveform and produced level is less than 0.5, the switching pattern remains unchanged. But, when the error reaches its peak value (errormax = 0.5), the switching pattern is changed to produce the next step, as shown in Figure 5 [20]. FIGURE 5Open in figure viewerPowerPoint Nearest-level based switching pattern of suggested 17-level topology The step-changing instant of ith voltage level (ti) can be calculated from Equation (5). Note that Equation (5) presents the step-changing times of first quarter of switching cycle. The step-changing instants of 2nd, 3rd and 4th quarters can also be calculated based on symmetric nature of output voltage waveform. As seen from Table 4, the employment of nearest level technique reduces the operating frequency of semiconductors, which leads to suppressed switching losses. The simplicity as well as ease of implementation of nearest level technique has increased its popularity. t i = 1 ω arcsin ( i − 0.5 ) × V I N V m i = 1 , 2 , … , N P (5) TABLE 4. ON/OFF transitions of switches at each switching period and estimated operating frequency of switches Switch Number of ON/OFF Frequency [Hz] Switch Number of ON/OFF Frequency [Hz] S1 16 800 P1 16 800 S2 7 350 P2 7 350 S3 3 150 P3 3 150 H1 1 50 H3 1 50 H2 7 350 H4 7 350 To certify low-frequency operation of switches in nearest level technique, the total ON-OFF transitions of switches during each switching cycle have been presented in Table 4. It is noted that the H1 and H3 switches operate at fundamental frequency, while the other semiconductors operate at quite low switching frequencies. This leads to reduced switching losses. 5 LOSSES ANALYSIS AND DESIGN OF CAPACITORS 5.1 Losses analysis The losses occurred in switched-capacitor multilevel inverters can be classified to three main types, which are elaborated in the following. 5.1.1 Conduction losses The conduction losses usually happen at on-state resistance of switches and diodes (Ron), forward voltage drop of diodes (VFD) and equivalent series resistance of capacitors (RESR). Total conduction losses of the structure can be achieved from (6), where the Irms and Iave denotes the Root Mean Square (RMS) and average values of components' current, respectively [24]. P L o s s , C o n d = P C o n d , S w i t c h e s + P C o n d , D i o d e s + P C o n d , C a p a c i t o r s = = R o n S w i t c h I r m s , S w i t c h 2 + R o n D i o d e I r m s , D i o d e 2 + V F D I a v e , D i o d e + R E S R × I r m s , C a p a c i t o r 2 (6) 5.1.2 Switching losses The switching losses happen during ON-OFF transitions of semiconductors. The switching losses depends on voltage stress (VS) and current stress (IStress), rising time (tr) and falling time (tf) and switching frequency (fs) of semiconductors, as (7). In this study, the employment of nearest level modulation technique has reduced the switching frequency of switches, which suppress the switching losses [24]. P L o s s , S w i t c h i n g = 1 6 f s V S I S t r e s s ( t r + t f ) (7) 5.1.3 Voltage ripple loss of capacitors Besides the conduction losses that happen at ESR of capacitors, the voltage ripple of capacitors is another source of loss, which is called “voltage ripple loss” of capacitors. This kind of loss can be computed from (8), where fs: switching frequency, C: capacitance of capacitor, ΔVRipple: voltage ripple of capacitor [24]. P L o s s , R i p p l e = 1 2 f s C ( Δ V R i p p l e ) 2 (8) 5.2 Capacitor design The voltage ripple of capacitors is an important factor that affects the capacitor losses as well as output voltage quality (and THD). The long discharging intervals of capacitors lead to higher ripples, higher losses and lower output voltage quality. The voltage ripple on capacitors can be limited by suitable design of capacitances. In this paper, the capacitances have been selected based on (9–10) [24], where Io: magnitude of the output current, cos(φ): load power factor, [tstart − tend]: longest discharging interval of capacitors, ΔVRipple: maximum allowable voltage ripple of capacitors Δ Q C = C × Δ V R i p p l e = ∫ t s t a r t t e n d I o sin ( ω t ) × cos ( φ ) d t (9) C ≥ ∫ t s t a r t t e n d I o sin ( ω t ) × cos ( φ ) d t Δ V R i p p l e (10) 6 COMPARISONS To verify the claimed properties, the suggested topology is compared with novel configurations presented in [19-24] from aspects of voltage gain, number of output voltage levels (NLevel), sources (NSource), capacitors (NCapacitor), switches (NSwitch), MOSFETs (NMOSFET), gate-driver circuits (NDriver), total devices (NDevice), and total voltage stress. Also, some conventional topologies [19-24] and the proposed topology have been compared from economic viewpoint through a CF. Various definitions have been presented for CF in literature, like [23, 24, 30]. This study considers the definition presented in [23], as (11), where the ‘α’ denotes the weight coefficient of total voltage stress [23]. C F = ( N M O S F E T + N D i o d e + N D r i v e r + N C a p + α T V S ) N S o u r c e (11) Table 5 and Figure 6 show the comparison results. Based on Figure 6a, despite using single DC source, the suggested and [19, 21, 24] topologies produce more steps (or gains) than others. This leads to a compact, cheap, and light structure. Also, to achieve equal steps, the proposed configuration requires less switches, MOSFETs and gate driver circuits than others (see Figure 6b,c). This property leads to reduced size and simple structure. As evident from Figure 7a,b, in wide range, the proposed configuration requires less number of capacitors and diodes than [20-24] to obtain equal number of steps. The reduction in diodes count will lead to reduced losses and improved efficiency. TABLE 5. Comparison statistics Topology [19] [20] [21] [22] [23] [24] Proposed NLevel 2(3n)+1 12n+1 12n+1 8n+1 8n+1 8n+1 2(n+2)+1 NMOSFET/IGBT 5n+4 14n 18n+5 12n 8n+2 20n-1 2n+6 NSwitch = NDriver 5n+4 11n 15n+4 10n 6n+2 20n-1 2n+6 NSource 1 2n 1 n n 1 1 NCapacitor 2n 2n 6n 2n 2n 4n-1 2n+1 NDiode n 14n 4n 0 n 3n 2n+1 NDevice 13n+9 43n 43n+10 25n 18n+4 47n-2 8n+15 Gain 3n 2 6n 2 2 4n 2(n+1) TVS 5.66(3n) 32n 42n-2 11n 16n+8 20n-1 12(2n)−1 Efficiency (%) Output power 92.1 244 W 95.3 60 W 97.2 900 W 80.6 15.5 W 95 400 W 88.9 74 W 94.2 235 W THD (%) 7.6 13-level 2.3 25-level 6.3 13-level N/A N/A 4 9-level 3.97 17-level FIGURE 6Open in figure viewerPowerPoint Comparison results for number of sources, switches, gate-driver circuits and MOSFETs: (a) NLevel vs. NSource; (b) NLevel vs. NSwitch and NDriver; (c) NLevel vs. NMOSFET FIGURE 7Open in figure viewerPowerPoint Comparative analysis on number of levels, capacitors and diodes: (a) NLevel vs. NCapacitor; (b) NLevel vs. NDiode Figure 8a,b confirms that with the same count of devices (NSource + NMOSFET + NDriver + NCapacitor + NDiode), the suggested structure can provide more steps and gains than the others. In the other words, to obtain the same gain or steps, the proposed topology requires fewer devices, which causes to have a compact, light, and cheap structure. FIGURE 8Open in figure viewerPowerPoint Comparisons on number of levels, number of devices and step-up capability: (a) Gain vs. NDevice; (b) Gain vs. TVS Based on Figure 9, while producing the same gains, less total voltage stress is imposed on semiconductors of proposed topology than other structures. This leads to reduced losses and improved efficiencies. Figure 10 displays the CF/NLevel of the proposed topology and [19-24] for different weighting coefficient of total voltage stress (α). It is seen that the CF/NLevel in the proposed topology is always less than that of other structures, which is a sign of reduced devices, low total voltage stress on semiconductors, and increased number of levels. FIGURE 9Open in figure viewerPowerPoint Gain comparison vs. TVS FIGURE 10Open in figure viewerPowerPoint CF/NLevel of structures in different values of α Table 5 presents the reported efficiency of topologies presented in [19-24] at their operation point (at a specific output power). It is seen that the proposed topology has better efficiency than other counter parts at equal output power levels. Also, the proposed topology has the second least THD among selected topologies. The low-THD of proposed topology is because of its high number of levels. 7 EXPERIMENTAL RESULTS To certify the feasibility of the proposed topology, the laboratory-scale prototype of the basic (17-level) structure has been implemented (Figure 11a). The nearest level technique (Figure 5) and the Atmega32 microcontroller have been employed for producing switching pulses. The setup parameters and device specifications have been presented in Table 6. Figure 11b shows the output voltage/current of the proposed basic topology for R-L load of R = 48 Ω and L = 120 mH. It is evident that the proposed basic topology has efficiently produced 8 positive, 8 negative, and zero (totally 17) steps. The peak load voltage and current are respectively about Vo,max ≈ 150 V, and Io,max ≈ 2.5A. So, the experimental gain of basic topology is about (Vo.max/VIN) ≈ 7.5. The difference between theoretical and experimental results originate from voltage drop on components (on-state resistance of semiconductors, forward voltage drops of diodes, ESR of capacitors). The phase difference of Δφ ≈ 38° seen between load voltage and current waveforms (validated by Δφ = arctan(Lω/R)) proves the capability of the proposed configuration on supplying R-L loads. According to Figure 11c, the THD (obtained from simulations done in PSCAD/EMTDC) of the output voltage is about 3.97%, which follows the IEEE519 standard (THD≤ 8%, Hi ≤ 5%). FIGURE 11Open in figure viewerPowerPoint Experimental setup and results: (a) laboratory prototype of proposed 17-level topology; (b) output voltage and current waveforms; (c) harmonic spectrum TABLE 6. Description of the experimental setup Parameter Value Input DC source VIN = 20[V] Frequency of reference waveform in nearest level fo = 50[Hz] MOSFETs IRFP260NPbF Diodes DSEP29-06A Optocoupler-driver TLP-250 Capacitances C1 = C2 = C3 = C4 = C5 = 4700[μF] Microcontroller ATmega32 Load R = 48[Ω], L = 120[mH] Oscilloscope GPS-1072B+ Figure 12 shows the dynamic performance of the proposed topology. It is observed that during load step-change from R = 100 Ω to R = 200 Ω, the load current is decreased to about half, and the output voltage increases just 2% to 2.5%. This certifies the appropriate dynamic performance of the proposed topology. FIGURE 12Open in figure viewerPowerPoint Dynamic performance of proposed topology during load step change from 113 to 60 W The voltage/current waveforms of C1–C5 have been presented in Figure 13. The results show that the voltage of C1–C5 has been naturally regulated on VC1 ≈ 20 V, VC2 = VC3 ≈ 40 V, VC4 = VC5 ≈80 V. FIGURE 13Open in figure viewerPowerPoint Voltage and current waveforms of capacitors The obtained results for voltage ripple of capacitors are ΔvC1 ≈ 1 V, ΔvC2 = ΔvC3 ≈ 1.2 V, and ΔvC4 = ΔvC5 ≈ 1.6 V. These small values obtained for voltage ripple confirm proper natural voltage balancing of capacitors. Also, the voltage/current waveform of capacitors (Figure 13) indicates that the charge/discharge process of capacitors has been uniformly distributed in the switching period. Based on Table 1, the charge/discharge process of C2 (or C4) is exactly the same as C3 (or C5). The only difference is that the C2 (or C4) is employed in positive voltage levels, but the C3 (or C5) is applied at the same negative voltage levels. So, the C2 (or C4) can be selected identical to C3 (or C5). That is why the voltage waveform, voltage ripple, and charge/discharge current waveform of C2 (or C4) is similar to that of C3 (or C5). The voltage waveform and voltage stress on semiconductors are shown in Figure 14 and Table 7. Figure 14 confirms that only H1 and H3 switches withstand Vo,max and the voltage stress on other semiconductors (especially the H1 and H3 as output switches) are much less than Vo,max. FIGURE 14Open in figure viewerPowerPoint Voltage waveforms of (a) diodes and (b) switches TABLE 7. Experimental results obtained for voltage stress (VS) on switches/diodes Switch VS [V] Switch VS [V] Diode VS [V] S1 20 P1 20 D1 20 S2 40 P2 40 D2 40 S3 80 P3 80 D3 40 H1 160 H3 160 D4 80 H2 40 H4 40 D5 80 Figure 15 displays the THD of the proposed structure at different modulation indexes. According to Figure 15, as the modulation index increases, the THD of converter decreases, which leads to higher qualities. Note that at low modulation indexes, the number of levels of proposed topology decreases, but it still operates as a multilevel inverter. FIGURE 15Open in figure viewerPowerPoint THD of the output voltage vs. modulation index Figure 16a shows the measured efficiency of suggested 17-level structure for different pure resistive loads of R = 210[Ω] (Po = 59[W]) to R = 48[Ω] (Po = 217[W]) (as worst condition). Figure 16a indicates that the efficiency of the converter is reduced by increment of the output power. Please note that much better efficiencies can be obtained by employing gallium nitride (GaN) or silicon carbide (SiC) semiconductors, which benefit from small on-state resistances. The efficiency of the proposed basic topology at operating point (R = 48[Ω] and L = 120[mH]) is about 94.2% (Figure 16b). The switching loss of diodes and MOSFETs are respectively PSw,Diodes ≈ 3.3[mW] and PSw,MOSFETs ≈ 13.7[mW]. The conduction loss of diodes and MOSFETs are respectively PCond,Diodes ≈ 8.5[W] and PCond,MOSFETs ≈ 4.7[W]. Also, the total power loss of capacitors is about PLoss,Capacitors ≈ 1.5[W]. It is seen that the employment of nearest level technique has limited the switching loss of semiconductors. FIGURE 16Open in figure viewerPowerPoint Efficiency analysis: (a) efficiency of proposed basic topology at pure resistive loads; (b) power losses at operating point (R = 48 Ω and L = 120 mH) Figure 17 shows the loss distribution (in watt and per cent) between switches, diodes, and capacitors at different output powers. FIGURE 17Open in figure viewerPowerPoint Detailed losses and the share of switches, diodes, and capacitors of total power loss at different output powers At low powers, the diodes and switches have almost the same losses. But as the output power increases, the loss of diodes becomes larger than that of switches. It is also seen from Figure 17 that the power dissipated in capacitors (due to their voltage ripple) smoothly increases by increment of output power. 8 CONCLUSIONS This paper proposes and developed a basic SCBMLI topology that can produce 17 steps and the voltage gain of 8 by means of only 1 DC source, 10 unidirectional switches, 5 capacitors, and 5 diodes. The proposed basic structure can be extended by extending the switched-capacitor stages to achieve higher voltage gains and levels. Due to the single-source nature of the proposed extended topology, it is expected to have less size, weight, and cost than other multi-source counterparts. The proposed generalized topology applies two half-bridges instead of a full-bridge (H-bridge) to create negative steps. Thus, only 2 switches (rather than 4 switches) are imposed to maximum voltage stress. This leads to less total voltage stress. Also, modularity, self-voltage balancing of capacitors, low voltage ripple on capacitors, and suitability for R-L loads are other main advantages of the proposed topology. Due to high quality and low THD of output voltage, the output filter can be eliminated or downsized. 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