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On-Chip Interconnection Architecture of the Tile Processor

2007; Institute of Electrical and Electronics Engineers; Volume: 27; Issue: 5 Linguagem: Inglês

10.1109/mm.2007.4378780

1937-4143

David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, B. Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John Brown, Anant Agarwal,

Advanced Memory and Neural Computing

IMesh, the tile processor architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. taking advantage of the five networks, the C-based ILIB interconnection library efficiently maps program communication across the on-chip interconnect. the tile processor's first implementation, the tile64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 Ghz.