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Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

2021; Elsevier BV; Volume: 120; Linguagem: Inglês

10.1016/j.microrel.2021.114120

1872-941X

Ivo Marques, Cristiano Rodrigues, Adriano Tavares, Sandro Pinto, Tiago Gomes,

Advanced Battery Technologies Research

This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two processor architectures at the instruction set architecture (ISA)-level. Lock-VA features an Arm Cortex-A9 with a RISC-V RV64GC, while Lock-VM includes an Arm Cortex-M3 along with a RISC-V RV32IMA processor. The solution explores field-programmable gate array (FPGA) technology to deploy softcore versions of the RISC-V processors, and dedicated accelerators for performing error detection and triggering the software rollback system used for error recovery. To test Lock-V in both versions, a fault-injection mechanism was implemented to cause bit-flips in the processor registers, a common problem usually present in heavy radiation environments.