SIDO coupled inductor‐based high voltage conversion ratio DC–DC converter with three operations
2021; Institution of Engineering and Technology; Volume: 14; Issue: 10 Linguagem: Inglês
10.1049/pel2.12130
ISSN1755-4543
AutoresZahra Saadatizadeh, Pedram Chavoshipour Heris, Ebrahim Babaei, Frede Blaabjerg, Carlo Cecati,
Tópico(s)Silicon Carbide Semiconductor Technologies
ResumoIET Power ElectronicsVolume 14, Issue 10 p. 1735-1752 ORIGINAL RESEARCH PAPEROpen Access SIDO coupled inductor-based high voltage conversion ratio DC–DC converter with three operations Zahra Saadatizadeh, Corresponding Author Zahra Saadatizadeh zsaadatizadeh@tabrizu.ac.ir Faculty of Electrical and Computer Engineering, University of Tabriz, 29th Bahman Blvd, Tabriz, Iran Correspondence Zahra Saadatizadeh, Faculty of Electrical and Computer Engineering, University of Tabriz, 29th Bahman Blvd, Tabriz, Iran Email: zsaadatizadeh@tabrizu.ac.irSearch for more papers by this authorPedram Chavoshipour Heris, Pedram Chavoshipour Heris Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, USASearch for more papers by this authorEbrahim Babaei, Ebrahim Babaei Faculty of Electrical and Computer Engineering, University of Tabriz, 29th Bahman Blvd, Tabriz, Iran Engineering Faculty, Near East University, 99138 Nicosia, North Cyprus, Mersin 10, TurkeySearch for more papers by this authorFrede Blaabjerg, Frede Blaabjerg Department of Energy Technology, Aalborg University, Aalborg, DenmarkSearch for more papers by this authorCarlo Cecati, Carlo Cecati Department of Information Engineering, Computer Science and Mathematics, University of L'Aquila, L'Aquila, ItalySearch for more papers by this author Zahra Saadatizadeh, Corresponding Author Zahra Saadatizadeh zsaadatizadeh@tabrizu.ac.ir Faculty of Electrical and Computer Engineering, University of Tabriz, 29th Bahman Blvd, Tabriz, Iran Correspondence Zahra Saadatizadeh, Faculty of Electrical and Computer Engineering, University of Tabriz, 29th Bahman Blvd, Tabriz, Iran Email: zsaadatizadeh@tabrizu.ac.irSearch for more papers by this authorPedram Chavoshipour Heris, Pedram Chavoshipour Heris Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, USASearch for more papers by this authorEbrahim Babaei, Ebrahim Babaei Faculty of Electrical and Computer Engineering, University of Tabriz, 29th Bahman Blvd, Tabriz, Iran Engineering Faculty, Near East University, 99138 Nicosia, North Cyprus, Mersin 10, TurkeySearch for more papers by this authorFrede Blaabjerg, Frede Blaabjerg Department of Energy Technology, Aalborg University, Aalborg, DenmarkSearch for more papers by this authorCarlo Cecati, Carlo Cecati Department of Information Engineering, Computer Science and Mathematics, University of L'Aquila, L'Aquila, ItalySearch for more papers by this author First published: 31 May 2021 https://doi.org/10.1049/pel2.12130Citations: 2AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinked InRedditWechat Abstract Here, a single-input, dual output (SIDO) coupled inductor-based high voltage conversion ratio DC–DC converter is proposed. The proposed converter has the capability of operating as a SIDO converter in a way that the terminal of the input voltage source is exchangeable among the three ports. Therefore, there are three different operation modes for the proposed converter. The voltage conversion ratios of the high voltage ports over the low voltage port can be improved by increasing the turn ratio of the coupled inductors. The main advantage of the proposed converter is achieving high voltage gains with lower number of components for the whole range of duty cycles comparing to the conventional multi-port high voltage gain converters. Moreover, two output voltages of the proposed converter can be simultaneously regulated on different constant levels with a good precision. In this study, the voltage conversion ratios, the inductors’ average currents, the voltage and current stress on the switches are calculated theoretically. Finally, an experimental prototype of 30 V input and 410, 260 V outputs with the power 510 W is implemented and the results are verifying the theoretical ones. 1 INTRODUCTION In recent years, the multi-port converters have been more interested for using in renewable energy systems such as photovoltaics (PV), fuel cells (FC), and also electric vehicles (EV) [1-3]. In the renewable energy systems, it is important to interface different levels of input and output DC voltages. As a result, dual-input, single-output (DISO) converters in [4-7] and single-input, dual-output (SIDO) converters in [8–11, 13–20] and single-input, three-output converter in [12] are presented. Multi-input converters are needed to be used in hybrid energy sources [4-7]. Multi-output converters can be used in off-grid solar home systems and should be able to supply the different electrical consumers with different levels of voltages and powers [12, 14]. Moreover, in the grid connected renewable energy sources, by using a series connected DC–AC inverter to the DC output voltage of DC–DC converter, the AC Bus 220 or 400 V with frequency of 50–60 Hz should be available for delivering power to the grid. On the other hand, considering that the extracted voltages from the renewable energy sources are at low levels, it should be better to increase the output voltage by using high voltage gain DC–DC converters [8, 12–16]. The presented multiport converters in [9–11, 17,18] have low voltage gains and almost equal to the conventional boost or buck converters. In order to increase the voltage gains in the multi-port converters, there are several approaches. In some converters, by using diode-capacitor cells, the output voltage is extended [8, 12]. In some cases, high voltage conversion ratio is achieved by applying coupled inductors, then the output voltages can be more extended by increasing the turns ratio of the coupled inductors [14-16]. In the case of multi-port DC–DC converters, similar to other DC–DC converters, having the low voltage stress on the semiconductor components leads to have low losses [8, 9, 12-16]. In the multi-output converters, the critical issue is to achieve the suitable precision of the output voltage regulations for all the output ports simultaneously under the variations of the input voltage level or output load. In the interleaved multi-port high voltage gain converters, there are at least two operating regions based on the duty cycle range. Then, these converters have complicated voltage controlling schemes [4, 6-11]. In [12], three high voltage gains are obtained using the switched-capacitor modules. In this converter, the voltages of the three output terminals cannot be regulated simultaneously. Similarly, the presented converters in [8, 14, 20] cannot be easily controlled, because these converters have just one controlling parameter of the duty cycle, where they have two voltage functions, which should be controlled. The presented SIDO converter in [20] has the capability of operating in a way that the terminal of the input voltage source is exchangeable between each of three ports. This converter suffers from low voltage gains, which is like the conventional boost and buck converters. Among the multi-port converters, some converters have boost and buck operations [21-24], buck and buck-boost operations [25], boost, buck-boost and buck operations [26, 27]. The presented converter in [27] has the reduced number of components but both of the input sources are not able to operate and transfer power at the same time. In this paper, a new coupled inductor-based single-input, dual output (SIDO) DC–DC converter is presented with the following merits; (i) the proposed converter has high voltage conversion ratio, (ii) the proposed converter has the capability of operating as a SIDO converter in a way that the terminal of the input voltage source is exchangeable among the three ports. This ability has made the converter suitable for versatile applications, (iii) there are three different operation modes for the proposed converter including boost, buck and buck and boost operations that have been explained in details separately, (iv) the voltage conversion ratios of the ports can be improved by increasing the turns ratio of the coupled inductors. As a result, the applied duty cycles to the active switches are not high, even if there is a high voltage gains needed at the load side, (v) comparing to the conventional SIDO converters, the proposed converter can provide high voltage gains with smaller number of components, (vi) the proposed converter has a good dynamic response towards the fluctuations of loads or the input voltage. In this paper, the proposed converter is analysed theoretically. Finally, the obtained analytical results, are reconfirmed by using the experimental results. 2 OPERATING PRINCIPLES OF THE PROPOSED CONVERTER The proposed converter is shown in Figure 1. Considering that the proposed converter has the three DC-ports, three SIDO operations exist for the proposed converter which can be modelled as Figure 2. FIGURE 1Open in figure viewerPowerPoint The power circuit of the proposed SIDO converter FIGURE 2Open in figure viewerPowerPoint The operations of the proposed converter; (a) flowchart; (b) boost operation; (c) buck operation; (d) boost-and-buck operation The operations of the proposed converter are categorized in Figure 2(a) and the power circuit of the proposed SIDO converter with the three operation modes are shown in Figure 2(b–d). Considering Figure 2(b–d), in the proposed converter, each of the three DC ports can be selected as the input voltage source and other two ports can be considered as output ports. In the proposed converter, the voltage V i is lowest DC voltage and the voltages V H 1 , V H 2 , are higher voltages V l < V H 2 < V H 1 . In the first operation of the proposed converter, the input voltage source is equal to V l and two output loads are R H 1 and R H 2 as shown in 2(b). Considering that the voltages V H 1 and V H 2 are higher than the input voltage (Vl), therefore, this operation can be defined as stepped-up operation. In the second operation of the proposed converter, the input voltage source is V H 1 and two output loads are R H 2 and R ℓ as shown in Figure 2(c). In this operation mode, the voltages V H 2 and V ℓ are lower than the input voltage source ( V H 1 ), therefore, it can be defined as stepped-down operation. The proposed converter in the third operation has the input voltage source equal to V H 2 and two output loads of and R ℓ as shown in Figure 2(d). Considering that one lower voltage ( V ℓ ) and R H 1 one higher voltage ( V H 1 ) than input voltage source ( V H 1 ) is obtained at the output ports, as a result, this operation is defined as stepped-up and stepped-down operation. Based on Figure 1, the power circuit of the proposed converter includes switches S1, S2, S3, S4, S5, and capacitor C1. Moreover, it has the first coupling inductor with two-winding transformer of T1, magnetizing inductance of L m 1 , leakage inductance of L k 1 and second coupling inductor with three-winding transformer of T2, the magnetizing inductance of L m 2 and leakage inductance of L k 2 . The first and second windings of the transformer T1 have n p 1 and n s 1 turns, respectively. As a result, the turn ratio of the transformer T1 is considered as n 1 = n s 1 / n p 1 . In the same way, the turns ratio of second transformer is considered as n 2 = n s 2 / n p 2 = n t 2 / n p 2 . The capacitor C1 is assumed to be large enough, so, the voltage across capacitor C1 would be constant as V C 1 . The switching pattern of switches and theoretical voltages’ and currents’ waveforms of the proposed converter in three operation modes are shown in Figure 3. FIGURE 3Open in figure viewerPowerPoint Switching pattern of switches and theoretical waveforms of proposed converter in three operation modes; (a) first operation; (b) second operation; (c) third operation. The voltages across the components in the three operations are same as each other. Therefore, in Figure 3(b,c) the waveforms of voltages are not shown to avoid showing repetitive waveforms. Considering Figure 3(a–c), it can be seen that only the direction of magnetizing inductors currents is changed in three operations. As an example, for the practical application of the experimental prototype of the converter, the input voltage source can be selected as a 30 V FC and the higher output voltages are V H 1 = 418.5 V and V H 2 = 262.5 V . The output voltages can be applied to DC/AC inverters (such as; LS Starvert iS7-750W 400V) to provide 220 V-AC at frequency of 50/60 Hz to supply the grid or off-grid consumers. Furthermore, the experimental prototype of the proposed converter can be utilized for some applications of an electric vehicle or in Green houses. 3 ANALYSIS OF THE PROPOSED CONVERTER DURING A SWITCHING PERIOD Based on Figure 3(a–c), the conducting interval time for the switch S1 is equal to D 1 T s and the switch S 2 is ON when the switch S 1 is OFF. The duty cycle of switches S 3 , S 5 is equal to D2 and the switch S4 is conducting when the switches S 3 , S 5 are OFF. In the analysis of the proposed converter, it is assumed that D 1 ≥ D 2 . Based on Figure 3, the currents of the inductances L m 1 and L m 2 have the maximum values ( I h 1 and I h 2 ) at t2 and t1 instants, respectively and minimum values ( I l 1 and I l 2 ) , at t0. Based on Figure 3, the proposed converter has three Modes during a switching period where the equivalent circuits are shown in Figure 4. FIGURE 4Open in figure viewerPowerPoint Equivalent circuit of the proposed converter during different modes in a switching period; (a) Mode 1; (b) Mode 2; (c) Mode 3. Mode 1 [ t 0 ≤ t ≤ t 1 ]: The equivalent power circuit of this Mode is shown in Figure 4(a). During this Mode, the switches, S 1 , S 3 and S 5 are conducting, while the switches S 2 and S 4 are OFF. Therefore, it should be written as v Im 1 = v L k 1 = V ℓ . Considering i L m 1 = I L k 1 , the voltage v L m 1 is obtained as v L m 1 = V ℓ / ( 1 + L k 1 / L m 1 ) . Moreover, the voltage v L m 2 is calculated as v L m 2 = ( V H 2 − V C 1 − V ℓ ) / n s 2 . Therefore, the currents of the magnetizing inductances are written as: i L m 1 = V ℓ / 1 + L k 1 / L m 1 t − t 0 / L m 1 + I l 1 (1) i L m 2 = V H 2 − V C 1 − V ℓ / n s 2 t − t 2 / L m 2 + I l 2 (2) S 2 Mode 2 [ t 1 ≤ t ≤ t 2 ]: Figure 4(b) shows the equivalent power circuit of this Mode. In this Mode, the switches, S 1 and S 4 are conducting, while the switches S 2 , S 3 and S 5 are OFF. Consequently, the voltage v L m 2 is calculated as v L m 2 = − V C 1 / ( 1 + n s 2 + k 2 ) . Therefore, the current i L m 2 should be as follows: i L m 2 = − V C 1 / 1 + n s 2 + k 2 / L m 2 t − t 1 + I h 2 (3)where, k 2 = L k 2 / [ L m 2 ( 1 + n s 2 ) ] . The inductor current i L m 1 is obtained from Equation (1). Mode 3 [ t 2 ≤ t < t 3 ]: Figure 4(c) shows the equivalent power circuit of this Mode. During this Mode, S 2 and S 4 are conducting, while the switches S 1 , S 3 and S 5 are OFF. Based on Figure 4(c), it can be concluded that i L k 1 = i L m 1 / ( 1 + n s 1 ) . Accordingly, the voltage v L m 1 is calculated as ( V C 1 + V ℓ − V H 1 ) / ( 1 + n s 1 + k 1 ) . As a result, the current i L m 1 is calculated as follows: i L m 1 = [ ( V C 1 + V ℓ − V H 1 ) / ( 1 + n s 1 + k 1 ) / L m 1 ] ( t − t 2 ) + I h 1 (4)where, k 1 = L k 1 / [ L m 1 ( 1 + n s 1 ) ] . The voltage v L m 2 and current i L m 2 is calculated with the same equations as in Mode 2. 4 VOLTAGE GAIN AND VOLTAGE ON CAPACITOR By considering the average voltage balance law of the inductors in steady state, the average voltages of v L m 1 , v L m 2 , v L k 1 and v L k 2 during single switching period should be equal to zero. Therefore, the Equations (5)–(7) are as follows: v ∼ L m 1 = D 1 V ℓ 1 + L k 1 / L m 1 + ( 1 − D 1 ) V C 1 + V ℓ − V H 1 1 + n s 1 + k 1 = 0 (5) v ∼ L m 2 = D 2 V H 2 − V C 1 − V ℓ n s 2 + ( 1 − D 2 ) ( − V C 1 ) 1 + n s 2 + k 2 = 0 (6) v ∼ L m 2 + v ∼ L k 2 = D 2 V ℓ − ( 1 − D 2 ) ( 1 + k 2 ) V C 1 1 + n s 2 + k 2 = 0 (7) By considering Equation (7), V C 1 / V ℓ can be calculated as follows: V C 1 / V ℓ = ( 1 + n s 2 + k 2 ) D 2 / [ ( 1 + k 2 ) ( 1 − D 2 ) ] (8) As a result, the voltage conversion ratio of s is calculated as follows: G 1 = V H 1 V ℓ = 1 + D 1 1 − D 1 1 + n s 1 + k 1 1 + L k 1 / L m 1 + D 2 1 − D 2 1 + n s 2 + k 2 1 + k 2 (9) Based on Equations (6) and (7), the voltage conversion ratio of G 2 is calculated as follows: G 2 = V H 2 V ℓ = 1 + n s 2 + k 2 ( 1 − D 2 ) ( 1 + k 2 ) = V C 1 D 2 V ℓ (10) By neglecting the leakage inductances of the coupled inductors, the voltage conversion ratio equations can be simplified as G 2 = ( 1 + n s 2 ) / ( 1 − D 2 ) and G 1 = 1 + [ D 1 / ( 1 − D 1 ) ] ( 1 + n s 1 ) + [ D 2 / ( 1 − D 2 ) ] ( 1 + n s 2 ) . In Figure 5(a,b), radar chart and 3D plot of the voltage conversion ratio of Port 2 with the calculated voltage gain of G 1 considering the number of turn ratio of the coupled inductors along with the duty cycle of the switches is shown to demonstrate the effects of these parameters on the voltage gain of the Port 2. From Figure 5(b), it can be seen that the Port 2 of the proposed converter has the largest operational area (shown in blue) for providing conversion ratios up to 20 times larger than the input voltage. In the same way, Figure 5(c,d) show the voltage conversion ratio of Port 3 which is calculated as G 2 considering the number of turn ratio of the coupled inductors with the duty cycle of the switches. From Figure 5(d), Port 3 of the proposed converter has the large operational areas (shown in blue and dark pink) for providing conversion ratios up to 10 times (blue area) and from 10 to 20 times (dark pink) larger voltages than the input voltage. FIGURE 5Open in figure viewerPowerPoint The voltage conversion ratios of the Ports 2 and 3 of the proposed converter ( G 1 , G 2 ) over the number of turn ratio of coupled inductors and duty cycle; (a) Radar chart for G 1 ; (b) 3D plot for G 1 ; (c) Radar chart for G 2 ; (d) 3D plot for G 2 In Figure 5, the number of turn ratio of the coupled inductors are considered the same values as n s 1 = n s 2 = n s and is considered variable as n s = 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 . Considering Equations (9)–(10), for an example in first operation mode, by using controlling parameter of duty cycle D 1 , the output voltage V H 1 can be regulated. Moreover, by using the controlling parameter of duty cycle D 2 , the output voltage of V H 2 is regulated. As a result, the output voltages V H 1 and V H 2 can be easily regulated at each preselected value. For controlling output voltages PI-controller is used. As shown in Figure 6, the switching controlling pulses of the output voltages would be produced. FIGURE 6Open in figure viewerPowerPoint Controlling block diagram of the output voltages of the proposed converter by using the switches; (a) controlling block of the output voltage V o 1 ; (b) controlling block of the output voltage V o 2 5 VOLTAGE STRESS ON SWITCHES Considering Figure 4(c), the voltage stress on switch S 1 during Mode 3 [ ( 1 − D 1 ) T s ] is obtained as follows: V S 1 = 1 + ( 1 + k 1 a ) [ G 1 − G 2 D 2 − 1 ] 1 + n s 1 + k 1 a V H 1 G 1 : D u r i n g ( 1 − D 1 ) T s (11) Moreover, the switch S 2 is turned off during Modes 1 ( D 2 T s ) and 2 [ ( D 1 − D 2 ) T s ] . Therefore, the voltage stress on the switch S 2 during Modes 1 and 2 is calculated as follows: V S 2 = 1 + G 2 + n s 1 k 2 a − G 2 D 2 1 G 1 V H 1 : D u r i n g D 2 T s (12) V S 2 = 1 + n s 1 k 1 a − G 2 D 2 1 G 1 V H 1 : D u r i n g [ ( D 1 − D 2 ) T s ] (13)where, k 1 a = 1 + ( L k 1 / L m 1 ) and k 2 a = 1 + ( L k 2 / L m 2 ) . The switch S 3 is turned off during Modes 2 and 3 [ ( 1 − D 2 ) T s ] . Therefore, Considering Figsure 4(b,c), the voltage stress on switch S 3 during Modes 2 and 3 [ ( 1 − D 2 ) T s ] is written as follows: V S 3 = V H 1 / [ ( 1 − D 2 ) G 1 ] : D u r i n g [ ( 1 − D 2 ) T s ] (14) The voltage stresses on switch S 4 during Mode 1 [ ( D 2 T s ) ] and switch S 5 during Modes 2 and 3, are obtained as follows: V S 4 = V H 2 : D u r i n g D 2 T s (15) V S 5 = V H 2 : D u r i n g ( 1 − D 2 ) T s (16) 6 AVERAGE CURRENTS OF SWITCHES, INDUCTORS AND THE OUTPUT CURRENTS Referring to Figure 1, the average currents passing through the switches S 1 , S 2 , S 3 , S 4 and S 5 during a switching period in steady state are calculated as follows: I S 1 = I L m 1 + ( 1 + n s 1 ) I H 1 = D 1 I L m 1 (17) I S 2 = − ( 1 − D 1 ) [ I L m 1 / ( 1 + n s 1 ) ] = I H 1 (18) I S 3 = I L m 2 + ( 1 + n s 2 ) I H 1 = [ I L m 2 − ( 1 + n s 2 ) I H 2 / D 2 ] D 2 (19) I S 4 = I S 5 = I H 2 (20) As a result, in the boost operating mode, the normalized current stress on switches based on the input current in the boost operating mode is calculated as follows: I S 1 , n = D 1 I L m 1 I i = D 1 ( 1 + n s 1 ) ( P o 1 / V o 1 ) / ( 1 − D 1 ) G 1 ( P o 1 / V o 1 ) + G 2 ( P o 2 / V o 2 ) D 1 ( 1 + n s 1 ) ( P o 1 / G 1 V i ) / ( 1 − D 1 ) G 1 ( P o 1 / G 1 V i ) + G 2 ( P o 2 / G 2 V i ) = D 1 ( 1 + n s 1 ) / ( 1 − D 1 ) 2 G 1 (21) I S 2 , n = − I o 1 / I i = 1 / ( 2 G 1 ) (22) I S 3 , n = 1 + n s 2 1 − D 2 D 2 2 G 1 + 1 2 G 2 (23) I S 4 , n = I S 5 , n = − I o 2 / I i = 1 / ( 2 G 2 ) (24) To calculate the normalized switches currents based on the input current I i = ( G 1 I o 1 + G 2 I o 2 ) in the above equations, the output powers of the converter P o 1 and P o 2 are considered equal to each other ( P o 1 = P o 2 ) . Accordingly, the RMS value of switches currents are calculated as follows: I S 1 − R M S , n = 1 T s ∫ 0 D 1 T s ( I S 1 , n ) 2 d t = I S 1 , n D 1 = D 1 ( 1 + n s 1 ) / ( 1 − D 1 ) 2 G 1 D 1 (25) I S 2 − R M S , n = I S 2 , n 1 − D 1 = 1 − D 1 / ( 2 G 1 ) (26) I S 3 − R M S , n = 1 + n s 2 1 − D 2 D 2 2 G 1 + 1 2 G 2 D 2 (27) I S 4 − R M S , n = I S 4 , n 1 − D 2 = 1 / ( 2 G 2 ) 1 − D 2 (28) I S 5 − R M S , n = I S 5 , n D 2 = 1 / ( 2 G 2 ) D 2 (29) Therefore, the average magnetizing inductance current of i L m 1 is calculated as follows: I L m 1 = ( 1 + n s 1 ) ( − I H 1 ) / ( 1 − D 1 ) (30) By considering the current balance law for the capacitor C 1 , the following equation can be written. i ∼ C 1 = D 2 ( I H 2 / D 2 ) + ( D 1 − D 2 ) I L m 2 / ( 1 + n S 2 ) + ( 1 − D 1 ) [ I L m 2 / ( 1 + n S 2 ) − I L m 1 / ( 1 + n S 1 ) ] = 0 (31) Accordingly, the average value of the inductor current of i L m 2 is calculated as follows: I L m 2 = − ( 1 + n S 2 ) ( I H 1 + I H 2 ) / ( 1 − D 2 ) (32) According to the power balance law in the proposed converter, I ℓ at the low voltage side would be obtained as; I ℓ = − ( G 1 I H 1 + G 2 I H 2 ) (33) The average currents of DC voltages I H 1 , I H 2 , I ℓ in the above equations are obtained based on the operation type. In the first operation, based on Figure 2(b), the output currents I o 1 and I o 2 are equal to I o 1 = − I H 1 = V H 1 / R H 1 and I o 2 = − I H 2 = V H 2 / R H 2 , respectively. The output powers should be written as P H 1 = V H 1 2 / R H 1 , P H 2 = V H 2 2 / R H 2 . The total output power ( P o T ) is equal to P o T = P H 1 + P H 2 . In the second operation, based on Figure 2(c), the output currents I o 3 and I o 2 are equal to I o 3 = − I ℓ = V ℓ / R ℓ and I o 2 = − I H 2 = V H 2 / R H 2 , respectively. The output powers would be obtained as P ℓ = V ℓ 2 / R ℓ , P H 2 = V H 2 2 / R H 2 . The total output power ( P o T ) is written as P o T = P ℓ + P H 2 . In third operation, considering Figure 2(d), the output currents I o 3 and I o 1 are equal to I o 3 = − I ℓ = V ℓ / R ℓ and I o 1 = − I H 1 = V H 1 / R H 1 , respectively. The output powers would be obtained as P ℓ = V ℓ 2 / R ℓ and P H 1 = V H 1 2 / R H 1 . The total output power ( P o T ) is equal to P o T = P ℓ + P H 1 . The currents’ ripple of the magnetizing inductances are Δ i L m 1 = [ V ℓ / ( 1 + L k 1 / L m 1 ) ] D 1 T s / L m 1 and Δ i L m 2 = [ ( V H 2 − V C 1 − V ℓ ) / n s 2 ] D 2 T s / L m 2 . The maximum and minimum values of the inductor current i L m 1 is calculated as I h 1 = I L m 1 + Δ i L m 1 / 2 , I l 1 = I L m 1 − Δ i L m 1 / 2 , respectively. The maximum and minimum values of the inductor current i L m 2 is written as I h 2 = I L m 2 + Δ i L m 2 / 2 and I l 2 = I L m 2 − Δ i L m 2 / 2 , respectively. 7 DESIGN CONSIDERATIONS In order to achieve continuous conduction mode (CCM) operation of the proposed converter, the average value of the currents passing through the inductances L m 1 and L m 2 has to be higher than the half of their current ripples. As a result, the following inequalities has to be verified. L m 1 > [ ( 1 − D 1 ) D 1 V ℓ ] / [ 2 ( 1 + n S 1 ) ( − I H 1 ) f s ] (34) L m 2 > ( V H 2 − V C 1 − V ℓ ) D 2 ( 1 − D 2 ) − 2 n S 2 ( 1 + n S 2 ) ( I H 2 + I H 1 ) f s (35) Considering [12], to obtain the more accurate designing of capacitors, then, the peak-to-peak value of the total voltage ripple which is mostly considered as Δ V C T = 0.01 V C is equal to sum of the voltage ripple across each capacitor ( Δ V C ) and voltage ripple caused by the ESR of capacitor ( Δ V C − E S R = r C Δ I C ) . As a result, the minimum value of capacitors for the maximum voltage ripple of them equal to Δ V C = 0.01 V C − r C Δ I C are calculated as given in Table 1. About the design of output capacitors, the hold-up time requirement for step-load response is also considered [12]. TABLE 1. Minimum values of capacitors C 1 _ min C 1 _ min = [ I H 2 / ( D 2 ) ] D 2 T s 0.01 V C 1 − r C [ I L m 2 / ( 1 + n S 2 ) − I H 2 / D 2 ] C H 1 _ min For boost and buck-boost operations C H 1 | E S R = I o 1 D 1 T s 0.01 V C H 1 − r C I L m 1 1 + n S 1 = D 1 R H 1 ( 0.01 − r C R H 1 1 1 − D 1 ) f s , C H 1 | T H T = ( V H 1 / R H 1 ) / [ 0.01 V H 1 ( 0.1 f s ) ] = 1 / [ 0.01 R H 1 ( 0.1 f s ) ] [ C H 1 − min = max ( C H 1 | E S R , C H 1 | T H T ) ] C H 2 _ min For boost and buck operations C H 2 | E S R = I o 2 ( 1 − D 2 ) T s 0.01 V C H 2 − r C I o 2 D 2 = 1 − D 2 R H 2 ( 0.01 − r C R H 2 1 D 2 ) f s , C H 2 | T H T = 1 / [ 0.01 R H 2 ( 0.1 f s ) ] , [ C H 2 − min = max ( C H 2 | E S R , C H 2 | T H T ) ] C ℓ _ min For buck and buck-boost operations C ℓ | min = { ( 1 − D 2 ) I o 3 − I L m 1 [ D 1 − D 2
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