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An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling

2021; Institute of Electrical and Electronics Engineers; Volume: 57; Issue: 1 Linguagem: Inglês

10.1109/jssc.2021.3104093

1558-173X

Timothy M. Hollis, Ronny Schneider, M. Brox, Thomas Hein, W. Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanović, Maksim Kuzmenka, Daniel Lauber, Juan Ocon-Garrido, David Ovard, K. Peter Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez-Gonzalez, Cristian Chetreanu, Andrea Sorrentino, Jörg Weller, Peter Mayer, Michael Richter, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong,

Low-power high-performance VLSI design

Demand for dynamic random access memory (DRAM) bandwidth has outpaced DRAM transistor performance. Given the options of major process investment to scale beyond sixth-generation graphics double-data-rate (GDDR6) or replace GDDR6 with costly high bandwidth memory (HBM), this article presents a solution that simultaneously increases pin and energy efficiency through the integration of four-level pulse amplitude modulation (PAM-4) into the single-ended memory interface. Building upon the existing GDDR6 architecture, evolutionary modifications to input, output, clocking, and data path, along with the component package design, enable a per-pin data rate of more than 22 Gb/s.