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A Custom Parallel Hardware Architecture of Nonlinear Model-Predictive Control on FPGA

2021; Institute of Electrical and Electronics Engineers; Volume: 69; Issue: 11 Linguagem: Inglês

10.1109/tie.2021.3118427

1557-9948

Fang Xu, Zhongyi Guo, Hong Chen, Dongdong Ji, Ting Qu,

Advanced Control Systems Design

This article presents the field-programmable gate array (FPGA) implementation of a particle swarm optimization (PSO)-based nonlinear model-predictive control (NMPC) for applications with millisecond timescales and resource-constrained embedded systems. A custom hardware circuit architecture of an NMPC controller, which mainly includes phase-locked loop clock, universal asynchronous receiver transmitter interface, trigonometric function, random number generator, objective function, and PSO solver modules, is implemented on the FPGA based on a hardware description language specification. It employs parallelism, pipelining, and specialized numerical formats to enhance the online computation performance of NMPC. In addition, the partial parallel expansion calculations of the fitness (objective) function and the particle position update are adopted for trading off the computational performance against resource usage. The hardware-in-the-loop experimental results through controlling a wheeled mobile robot model demonstrate that the design is capable of computing the required control action in real time by using a midrange FPGA, while still offering good control performance.