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An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

2022; Institution of Engineering and Technology; Volume: 16; Issue: 4 Linguagem: Inglês

10.1049/cds2.12112

1751-8598

Hamid Mahmoodian, Mehdi Dolatshahi, S. Mohammadali Zanjani, Mohammad Amin Honarvar,

Low-power high-performance VLSI design

IET Circuits, Devices & SystemsVolume 16, Issue 4 p. 360-371 ORIGINAL RESEARCHOpen Access An energy-efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications Hamid Mahmoodian, Hamid Mahmoodian Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, IranSearch for more papers by this authorMehdi Dolatshahi, Corresponding Author Mehdi Dolatshahi dolatshahi@iaun.ac.ir orcid.org/0000-0002-5948-7277 Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran Correspondence Mehdi Dolatshahi, Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran. Email: dolatshahi@iaun.ac.irSearch for more papers by this authorS. Mohammadali Zanjani, S. Mohammadali Zanjani Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran Smart Microgrid Research Centre, Najafabad Branch, Islamic Azad University, Najafabad, IranSearch for more papers by this authorMohammad Amin Honarvar, Mohammad Amin Honarvar Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, IranSearch for more papers by this author Hamid Mahmoodian, Hamid Mahmoodian Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, IranSearch for more papers by this authorMehdi Dolatshahi, Corresponding Author Mehdi Dolatshahi dolatshahi@iaun.ac.ir orcid.org/0000-0002-5948-7277 Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran Correspondence Mehdi Dolatshahi, Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran. Email: dolatshahi@iaun.ac.irSearch for more papers by this authorS. Mohammadali Zanjani, S. Mohammadali Zanjani Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran Smart Microgrid Research Centre, Najafabad Branch, Islamic Azad University, Najafabad, IranSearch for more papers by this authorMohammad Amin Honarvar, Mohammad Amin Honarvar Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, IranSearch for more papers by this author First published: 02 March 2022 https://doi.org/10.1049/cds2.12112AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinked InRedditWechat Abstract In this paper, a latch-based energy-efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre-amplifier and latch. The latch stage is designed for the main purpose of low-power consumption and high-speed performances. The proposed speed-up technique for the latch structure controls the threshold voltage (Vth) of the cross-coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double-tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double-tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed-up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high-resolution (up to 12 bit) and high-speed low-power analogue-to-digital converter applications. Moreover, the effects of the non-ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte-Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs. 1 INTRODUCTION Comparators are considered as the important building blocks in data converters, such as successive approximation register (SAR) and pipe-line analogue-to-digital converters (ADCs). Among different types of comparators, dynamic comparators which are working based on the positive feedback structure are very popular and have many applications in the recent ADC circuits. Moreover, these comparators benefit from the lower power consumption than other types of comparators and are preferred in many new types of data converters, such as novel flash, pipe-line and SAR ADCs [1]. Based on their application, a pre-amplifier stage is sometimes added to the comparator structure to extend the voltage difference between the two input signals to achieve a higher resolution [1]. Besides power consumption, other parameters such as speed, sensitivity (comparator accuracy), input-referred voltage error and kickback noise, are considered as the major performance measures for the performance comparison of different comparator topologies [1-4]. Many studies have been carried out to improve one or more of the abovementioned parameters or to provide different circuit techniques to improve the overall performance of the whole comparator circuit [5-10]. However, due to the disadvantages of the conventional dynamic comparators including: high delay, high dynamic power consumption and input-referred voltage errors; the designers have led to the development of the modified double-tail dynamic comparators [5]. However, in order to improve the speed/accuracy trade-off of low-power ADCs, the improvement in the speed performance and power consumption of the double-tail dynamic comparators has drawn the most attention of the analogue integrated circuits designers [11-15]. In the recent years, various approaches have been discussed in [16-23], to improve the input offset performance of the comparators. Moreover, the reduction of the input-referred noise has been addressed in [24, 25]. In [1, 8-14] and [26-28], the positive feedback circuit has been added to the core body of the pre-amplifier stage to significantly reduce the comparator response time (delay). However, the positive feedback circuit itself increases both the power consumption as well as the input-referred noise [1]. For example, in [1], two transistors are utilised in series with the input differential pair as control switches in the pre-amplifier stage, to control the power consumption of the circuit. However, a larger chip area, incapability to operate in low supply voltages, and high input-referred noise due to the use of positive feedback block in the pre-amplifier stage, are the major disadvantages of the designs reported in [1, 8-14]. On the other hand, realising the integrated circuits in the sub-threshold region and bulk-drive techniques are the main two approaches that significantly reduce the power consumption, while increase in the delay of the circuit can be considered as a reduction in the speed performance. In addition, the supply boosting approach is another technique that is used in the realisation of low-voltage circuits [13]. However, the mismatch existence between the transistors and the offset voltage error are two other important issues in the comparator design in the nanometre technologies. For negligible mismatch effects, larger transistors have to be selected; this increases the parasitic capacitances and leads to the slower charging and discharging of the capacitors. Moreover, larger transistor dimensions themselves increase the transconductance of the transistor, which results in a faster speed for the comparators. Therefore, the delay time decreases, while the dynamic power consumption increases with larger capacitances, and the circuit occupies a large chip area. Although the dynamic power consumption is significantly reduced by the lower supply voltage, the reduction in drain currents of the transistors increases the delay of the comparator. On the other hand, the deep sub-micron technologies suffer from high leakage currents, which leads to a higher leakage power consumption [29]. Furthermore, in these technologies, the threshold voltage is not reduced accordingly with the supply voltage reduction, so the reductions in supply voltage and power consumption may result in serious design challenges. These challenges have attracted the designers' attention to other emerging technologies [30]. An alternative to the conventional CMOS technology is the Carbon Nanotube Field Effect Transistor (CNTFET) technology. Therefore, the proposed comparator in this paper is designed in CNTFET technology. It is worth mentioning that, unlike previous designs, only four transistors are added to a conventional double-tail comparator circuit to automatically control the threshold voltage of the inverters utilised in the proposed latch stage. As a result, the delay of the proposed comparator is reduced without imposing extra values of power consumption. The reduced delay value allows the proposed comparator to operate in high-speed applications up to 15 GHz, with a low power consumption in the scale of micro-watt (µW). This paper is organised as follows: In Section 2, the physical and electrical characteristics of the CNTFET technology are introduced. The performance of the conventional double-tail dynamic comparators and some previously reported comparator designs are reviewed in Section 3. In Section 4, the proposed comparator circuit is discussed in detail. Section 5 presents the simulation results of the proposed circuit in CNTFET technology. Finally, Section 6 compares the simulation results with other previously reported designs and presents the concluding remarks. 2 A BRIEF REVIEW ON CARBON NANOTUBE FIELD EFFECT TRANSISTOR TECHNOLOGY CNTFETs have an improved off-state leakage current compared to the conventional MOSFET transistors in CMOS technology [31]. Therefore, a larger ratio of on-state current to off-state leakage current (ION/IOFF) can be obtained for the CNTFET devices [31-33]. Moreover, other advantages of CNTFETs, such as: ballistic transport of the carriers in low supply voltage, low power consumption and very small dimensions, enable CNTFETs to be considered as a proper alternative for replacing the CMOS technology in emerging high performance and high-density chips. These transistors can also exhibit ballistic transport of charge carriers between the source and drain terminals at higher speeds [34-37]. In other words, CNTFETs can have the similar physical structure as the MOSFETs, but with the only difference that in CNTFET the carbon nanotubes (CNT) between the drain and source terminals act as the conducting channels [38]. Nanotubes are formed by rolling up a graphene sheet along a vector which is called "chiral vector (n1, n2)" as shown in Figure 1. If n 1 − n 2 ≠ 3 k $\left({n}_{1}-{n}_{2}\right)\ne 3k$ , (where k $k$ is assumed as an integer number), the nanotube acts as a semiconductor. Otherwise, CNT acts as a metal [31-33]. FIGURE 1Open in figure viewerPowerPoint Graphene sheet and carbon nanotube basic structure [31] In addition, the nanotube diameter can be calculated based on the Equation (1): D C N T = a n 1 2 + n 1 n 2 + n 2 2 π ${D}_{CNT}=\frac{a\sqrt{{n}_{1}^{2}+{n}_{1}{n}_{2}+{n}_{2}^{2}}}{\pi }$ (1)where, a is the lattice constant, which is equal to 2.49 Å. The width of the CNT transistor can be calculated using Equation (2) as follows, W gate = MAX W min , ( N − 1 ) Pitch + D CNT ${\mathrm{W}}_{\text{gate}}=\text{MAX}\hspace*{.5em}\left({\mathrm{W}}_{\text{min}},(\mathrm{N}-1)\text{Pitch}+{\mathrm{D}}_{\text{CNT}}\right)$ (2)where, Wmin is the minimum gate width, N is the number of nanotubes, pitch is the distance between the two adjacent nanotube centres, and DCNT is the nanotube diameter [31, 32]. As reported in [38], the major advantage of the CNTFETs is their threshold voltage tunability. The threshold voltage of a CNTFET is inversely related to the diameter of the nanotube as it is given in Equation (3). V TH ≈ E g 2 e ≈ 3 3 a V π e D C N T ≈ 3 3 a V π e D C N T ≈ 5.5 n 1 2 + n 1 n 2 + n 2 2 ${V}_{\text{TH}}\approx \frac{{E}_{g}}{2e}\approx \frac{\sqrt{3}}{3}\frac{a{V}_{\pi }}{e{D}_{CNT}}\approx \frac{\sqrt{3}}{3}\frac{a{V}_{\pi }}{e{D}_{CNT}}\approx \frac{5.5}{\sqrt{{n}_{1}^{2}+{n}_{1}{n}_{2}+{n}_{2}^{2}}}$ (3)where, e is an electron charge, α is the scattering coefficient, Vπ (= 3.033 eV) is the carbon π–π bond energy, and , Eg is the bond energy, which is inversely related to the nanotube diameter [31-33]. Obviously, by increasing the values of the chiral vector, the threshold voltage of the transistor decreases according to Equation (3). 3 REVIEW ON THE DOUBLE-TAIL DYNAMIC COMPARATORS This section introduces some of the recent double-tail dynamic comparators while also reviewing their pros and cons. In subsection 3.1, a conventional double-tail dynamic comparator circuit is introduced, while subsections 3.2, presents the detailed descriptions of the recent reported designs discussed in [1], [11], and [26]. 3.1 Conventional double-tail dynamic comparator circuit Figure 2, shows the two stages of the dynamic comparator circuit, which include the pre-amplifier stage (input differential pair M1 and M2, the load transistors M3 and M4, and the current source Mtail1) and latch stage (two back-to-back inverters M7-M8 and M9-M10 and a tail transistor Mtail2). Transistors MR1 ​​and MR2 are used to discharge the output nodes in the reset phase. Moreover, the presence of MR1 and MR2 between the internal nodes (fn and fp) and the main outputs, reduces the kickback noise. The circuit performance is as follows: Pre-charge or Reset phase For CLK = 0, both the tail transistors Mtail1 and Mtail2 are off. However, M3 and M4 are on and pre-charge the fn and fp nodes through the parasitic capacitors seen at these nodes up to the supply voltage of VDD. Therefore, MR1 and MR2 are turned on to discharge the output nodes Outn and Outp to GND. Decision or Comparison phase For CLK = 1, both the tail transistors Mtail1 and Mtail2 are on, while M3 and M4 are off. When Mtail1 is turned on, the capacitors at fn and fp nodes discharge with different speeds (depending on whether VINP or VINN is greater). For the case that VINP greater than VINN, fn is discharged faster than fp. Therefore, MR2 turns off faster than MR1. When MR2 turns off, the voltage at Outp increases, while the load capacitor CL is charged through M8. When the load capacitor of Outp is charged to the threshold voltage, the NMOS transistor of the opposite inverter, that is, M9, turns on and discharges the node Outn to GND. The delay of the comparator circuit is directly related to the value of the load capacitance, while it is inversely related to the differential input voltage (∆Vin), Itail2, common-mode input voltage, and the transconductances of MR1 ​​and MR2 transistors. However, the main drawback of the conventional double-tail dynamic comparator is the high static power consumption due to the presence of MR1 and MR2 in the decision phase [1]. FIGURE 2Open in figure viewerPowerPoint The conventional double-tail dynamic comparator [1] 3.2 Recently reported double-tail dynamic comparator designs In a conventional double-tail dynamic comparator circuit, the capacitors seen at the fn and fp nodes are fully discharged in the decision phase. Therefore, fn and fp are pre-charged to the supply voltage during the reset phase which leads to a higher energy consumption during each conversion. The circuit presented in [1], besides with higher operating speed, has a lower power consumption due to the prevention of discharge in the internal nodes. The use of positive feedback in the pre-amplifier circuit increases the pre-amplifier speed which decreases the delay of the comparator. However, this considerably increases the kickback noise compared to the conventional dynamic comparator structure. The structure proposed in [1] still consumes static power due to the existence of path between the power supply and the ground (GND) through MR1 and MR2 and pull-up transistors in the latch stage. Moreover, in the decision phase for the circuit discussed in [1], the presence of the positive feedback transistors in the pre-amplifier circuit along with the differential pair and Mtail1 create a direct path between the power supply and ground, so the energy consumption of the comparator increases. To mitigate this drawback, switch transistors (Msw1,2) are added to the pre-amplifier stage to cut the static current path in the decision phase. In the pre-amplifier stage of the design discussed in [11], the voltage variation range is limited to VDD/2 in order to reach the low power performance for the comparator. Besides, in this circuit, the input common-mode voltage level in the latch stage is increased to VDD/2, in order to meet a faster speed performance in this stage. Therefore, a higher speed is achieved in this comparator compared to the conventional double-tail dynamic comparator. In the reset phase, the output voltage of the pre-amplifier stage is pre-charged to VDD/2. This value can activate the second stage, leading to a static power consumption in the circuit. The voltage swing of the pre-amplifier stage is limited, so the power consumption of the circuit is considerably reduced (by a factor of 50%). Moreover, by using this approach, the time required to charge the output nodes of the pre-amplifier stage to the threshold voltage of the NMOS transistors in the latch stage is reduced, so, the circuit delay decreases and the speed of the comparator increases. Although the technique used in this circuit is efficient, the proper operation of the latch stage in the recent deep sub-micron technologies with a supply voltage of less than 1 V faces many severe challenges due to the stack limitations of four transistors in this stage. Moreover, this design has a high kickback noise compared to other designs, because of the considerable capacitance values located between the output and input nodes. In [26], a hybrid double-tail comparator is proposed to reach the high-speed and low-power performances. Similar to the structure discussed in [1], the pre-amplifier stage includes a positive feedback structure. But, the latch structure is formed by eliminating the tail transistors and reset transistors (MR1, ​​and MR2) and substituting them with two transistors, which are controlled by the output nodes of the pre-amplifier. The structure proposed in [26], has a high operation speed due to the positive feedback in the pre-amplifier stage, but, it has a higher power consumption compared to the conventional double-tail dynamic comparator. Additionally, the positive feedback in the pre-amplifier stage results in a high kickback noise compared to the conventional double-tail structure. 4 THE PROPOSED DOUBLE-TAIL DYNAMIC COMPARATOR In the proposed circuit presented in this paper, the decision speed is enhanced by utilising only four transistors in the latch circuit of a conventional double-tail dynamic comparator structure. Moreover, the use of CNTFETs enables the designer to reduce the delay in turning on M9 (M10) by adjusting the threshold voltage of the transistors in the double-tail dynamic comparators (Figure 2). Figure 3, illustrates the overall design of ​​the proposed circuit in which M3 and M4 are added to a basic inverter structure and their drain terminals are connected to the body terminals of M1 and M2, respectively. FIGURE 3Open in figure viewerPowerPoint The proposed basic automatic threshold voltage control structure FIGURE 4Open in figure viewerPowerPoint Threshold voltage variations of the Carbon Nanotube Field Effect Transistor (CNTFET) versus VSB The performance of the proposed circuit is as follows: When the input signal (fp) increases, VOUTn decreases while VDD-VOUTn increases, and for VDD-VOUTn ≥ |VTH3|, M3 turns on. Therefore, VSB1 = –VDD; moreover, from Figure 4, the threshold voltage of M1 for chiral vector (19, 0) decreases by 25% compared to that in Vth0. Consequently, the output of the inverter has a faster pull-down process time. Besides the abovementioned approach, as mentioned in Section 2, a proper chiral vector should be selected for the inverter transistors to reduce their threshold voltage and enhance the decision speed. Figure 5, shows the proposed circuit in which the comparator delay time is reduced using the concept of the ​​automatic threshold voltage control. The pre-amplifier stage consists of M1-M4 and the tail transistor (Mtail1). Moreover, M7-M10 are forming the two back-to-back inverters. Transistors M11-M14 are the switches which activate the speed-up circuit that can automatically shift the voltage transfer characteristic (VTC) of the inverters to the left or right. Transistors MR1 and MR2 separate the pre-amplifier stage from the latch stage to effectively reduce the kickback noise. FIGURE 5Open in figure viewerPowerPoint The proposed speed boosting approach employed in the proposed comparator Considering the speed of the comparator, the operation of the circuit can be explained as follows: If the input VINp is greater than VINn in the pre-amplifier circuit, the voltage at fn node discharges faster, and if fn voltage becomes less than the threshold voltage of MR2, then MR2 turns off. Then, VOUTp charges faster up to the threshold voltage of M9, which turns on M9 and pulls VOUTn down towards GND. Meanwhile, VOUTn discharges to VDD-VOUTn ≥ VTH11, that is, M11 turns on and the source-bulk voltage of M9 becomes –VDD to reduce its threshold voltage. Therefore, M9 pulls VOUTn down faster than the conventional comparator circuits. Moreover, by increasing VOUTp voltage level, M14 turns on and the source-bulk voltage of M8 becomes VDD. This reduces the threshold voltage of M8, while VOUTp charges to "1" logic faster. The overall power consumption of the circuit can be expressed as Equation (4). In this equation, P p r e ${P}_{pre}$ is the dynamic power which is consumed by the pre-charging process at fn and fp nodes, P l a t c h ${P}_{latch}$ is the power consumed by the back-to-back inverters of the latch stage, and P t r a n s ${P}_{trans}$ is the power consumption during the transition from the reset phase to the decision phase. P d i s s = P p r e + P l a t c h + P t r a n s ${P}_{diss}=\hspace*{.5em}{P}_{pre}+{P}_{latch}+{P}_{trans}\hspace*{.5em}$ (4) Due to the fact that the leakage current in CNTFET technology is very low [32, 33], the leakage power of transistors in the pre-amplifier stage in decision phase can be ignored, and P p r e ${P}_{pre}$ can be obtained using Equation (5). In this equation, f c l k ${f}_{clk\hspace*{.5em}}$ is the comparator clock frequency, R o n 3 ${R}_{on3}$ ( R o n 4 ${R}_{on4}$ ) are the on-state resistances of M3 (M4), respectively, and C f n ${C}_{fn}$ ( C f p ${C}_{fp}$ ) are the parasitic capacitances of the internal nodes. P p r e = 1 T ∫ 0 T 2 V D D I s u p p l y d t = f c l k V D D ∫ 0 1 2 f c l k I C f n ( f p ) d t = f c l k V D D 2 R o n 3 ( 4 ) ∫ 0 1 2 f c l k e − t R o n 3 ( 4 ) C f n ( f p ) d t ${P}_{pre}=\frac{1}{T}\underset{0{}}{\overset{\frac{T}{2}}{\int }}{V}_{DD}\hspace*{.5em}{I}_{supply}\hspace*{.5em}dt={f}_{clk\hspace*{.5em}}{V}_{DD}\hspace*{.5em}\underset{0{}}{\overset{\frac{1}{2{f}_{clk\hspace*{.5em}}}}{\int }}\hspace*{.5em}{I}_{Cfn(fp)}\hspace*{.5em}dt=\hspace*{.5em}\frac{{f}_{clk\hspace*{.5em}}{{V}_{DD}}^{2}}{{R}_{on3(4)}}\underset{0{}}{\overset{\frac{1}{2{f}_{clk\hspace*{.5em}}}}{\int }}\hspace*{.5em}{e}^{\frac{-t}{{R}_{on3(4)}{C}_{fn(fp)}}}\hspace*{.5em}dt$ (5) It is worth mentioning that the proposed latch circuit consumes the power mainly in the decision phase. At the beginning of the decision phase, M7 and M8 are on. Assuming that VINp is greater than VINn, at the end of t0, M9 turns on, and since M7 is turned on, the latch regeneration initiates and power is consumed due to the activation of the inverter (transistor pair M7 and M9). This power is consumed until tp (i.e., when M7 turns off). After tp, M7 turns off, and the current flows from the power supply corresponds only to M8. Considering the above facts and ignoring the leakage current of the transistors, the power consumption of the latch stage can be expressed as Equation (6). P l a t c h ≈ f c l k V D D ∫ T 2 T I M 7 + I M 8 d t ≈ f c l k V D D ∫ T 2 t 0 I M 7 d t + ∫ t 0 t p I i n v 7,9 d t + ∫ T 2 T I M 8 d t ${P}_{latch}\approx {f}_{clk\hspace*{.5em}}{V}_{DD}\hspace*{.5em}\underset{\frac{T}{2}{}}{\overset{T}{\int }}\hspace*{.5em}\left({I}_{M7}+{I}_{M8}\right)\hspace*{.5em}dt\approx \hspace*{.5em}{f}_{clk\hspace*{.5em}}{V}_{DD}\hspace*{.5em}\left[\underset{\frac{T}{2}{}}{\overset{{t}_{0}}{\int }}\hspace*{.5em}{I}_{M7}\hspace*{.5em}dt+\underset{{t}_{0}{}}{\overset{{t}_{p}}{\int }}\hspace*{.5em}{I}_{inv7,9}\hspace*{.5em}dt+\underset{\frac{T}{2}{}}{\overset{T}{\int }}\hspace*{.5em}{I}_{M8}\hspace*{.5em}dt\right]$ (6) Since, in the VTC curve of the inverter, the time for changing the inverter state (tp-t0) is considered to be very short, the second term in Equation (6) can be ignored and after some mathematical simplifications the latch power consumption can be expressed as Equation (7). P l a t c h ≈ f c l k V D D ∫ T 2 t 0 C L d V o u t n d t d t + ∫ T 2 T C L d V o u t p d t d t ≈ f c l k V D D C L V t h 10 + V D D ${P}_{latch}\approx \hspace*{.5em}{f}_{clk\hspace*{.5em}}{V}_{DD}\hspace*{.5em}\left[\underset{\frac{T}{2}{}}{\overset{{t}_{0}}{\int }}\hspace*{.5em}{C}_{L}\frac{d{V}_{outn}}{dt}\hspace*{.5em}dt+\hspace*{.5em}\underset{\frac{T}{2}{}}{\overset{T}{\int }}\hspace*{.5em}{C}_{L}\frac{d{V}_{outp}}{dt}\hspace*{.5em}dt\hspace*{.5em}\right]\approx {f}_{clk\hspace*{.5em}}{V}_{DD}{C}_{L}\left[{V}_{t{h}_{10}}+VDD\right]$ (7) As it is mentioned in the previous section, the tail transistor of the latch turns ON from the beginning of the decision phase until the voltage level of the fn (fp) nodes are greater than the threshold voltage value of MR1 (MR2), that is, during t 0 ${t}_{0}$ . However, this has no significant effect on the performance of the latch stage, and only increases the power consumption. Therefore, the power for the transition from reset phase to decision phase, which results from the current shown in Figure 6, can be calculated as it is expressed in Equation (8). P t r a n s ≈ f c l k V D D ∫ t O N − t a i l 2 t 0 I t a i l 2 d t ≈ f c l k V D D I t a i l 2 2 C L V t h 9 ( 10 ) I t a i l 2 − t O N − t a i l 2 ${P}_{trans}\approx {f}_{clk\hspace*{.5em}}{V}_{DD}\hspace*{.5em}\underset{{t}_{ON-tail2}{}}{\overset{{t}_{0}}{\int }}\hspace*{.5em}\left({I}_{tail2}\right)\hspace*{.5em}dt\approx {f}_{clk\hspace*{.5em}}{V}_{DD}{I}_{tail2}\hspace*{.5em}\left(\frac{2{C}_{L}{V}_{t{h}_{9(10)}}}{Itai{l}_{2}}-{t}_{ON-tail2}\right)$ (8) FIGURE 6Open in figure viewerPowerPoint The current path through the latch stage during the transition time from reset to decision phases In fact, to reduce the transition dynamic power, Mtail2 must be turned on after turning MR1 (MR2) off, which means that the terms in the above parenthesis at the right side of Equation (8), are approximately zero. Giving the above facts, the final circuit structure of the proposed comparator is shown in Figure 7. In this structure, Mtail2 (see Figure 6) is substituted by two parallel transistors, Mtail2p and Mtail2n, which are controlled by the voltages at the nodes of fp and fn, respectively. Therefore, the leakage current path during the mentioned transition is cut and the energy per conversion (EPC) is reduced effectively. In designing Mtail2p and Mtail2n, the proper sizing of these transistors is very important, since they have to use a current with the value of half of the drain current of Mtail2, once they turn on. In addition, by adjusting the threshold voltage of these transistors and MR1 ​​and MR2, the EPC (i.e., the term P t r a n s $\hspace*{.5em}{P}_{trans}$ ) value can be controlled and reduced effectively. Note that in this design adjusting the threshold voltage of transistors by varying the nanotube diameter can be considered as an advantage of employing the CNTFET technology. FIGURE 7Open in figure viewerPowerPoint The complete proposed comparator