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Gate Capacitance Characterization of Silicon Carbide and Silicon Power mosfets Revisited

2022; Institute of Electrical and Electronics Engineers; Volume: 37; Issue: 9 Linguagem: Inglês

10.1109/tpel.2022.3164360

1941-0107

Roger Stark, Alexander Tsibizov, Ivana Kovacevic-Badstuebner, Thomas Ziemann, Ulrike Großner,

Advancements in Semiconductor Devices and Circuit Design

Capacitance–voltage (C–V) gate characteristics of power metal-oxide-semiconductor field-effect transistors ( mosfet s) play an important role in the dynamic device performance. C–V characterization of the mosfet gate structure is a necessary step for evaluating the mosfet switching behavior and calibrating lumped equivalent capacitances of mosfet compact models. This article presents a comprehensive analysis on gate C–V measurements of silicon (Si) and silicon carbide (SiC) power mosfet s leading to clear measurement guidelines. The requirements on the measurement setup, the selection of equivalent models used for the mosfet capacitance extraction, and the measurement frequency range are defined and supported by an accurate C–V characterization of several Si- and SiC power mosfet s. The results show that the gate-source and gate-drain capacitances should be extracted at a frequency of some 10 kHz rather than at 1 MHz, as typically adopted in datasheets, to avoid parasitic effects introduced by the measurement setup and package. Furthermore, analytical expressions for $C_\text{dg}$ and $C_\text{sg}$ were derived based on a lumped equivalent circuit, which explain the influence of the measurement setup and the package parasitics on the C–V measurements. Nonideal measurement conditions are identified and correlated to the differences in C–V extraction with either parallel or series-equivalent model. A new method is proposed to estimate the ratio of the mosfet 's on -state resistance components $R_\text{ch}$ and $R_\text{drift}$ based on the presented C–V measurement guidelines, which are applicable to all three- and four-terminal power mosfet s.