Portal de Periódicos da CAPES

Fermi-Level Pinning at the Polysilicon/Metal Oxide Interface—Part I

2004; Institute of Electrical and Electronics Engineers; Volume: 51; Issue: 6 Linguagem: Inglês

10.1109/ted.2004.829513

1557-9646

C. C. Hobbs, L. R. C. Fonseca, A. A. Knizhnik, V. Dhandapani, S. Samavedam, W. Taylor, J. M. Grant, L. Dip, Dina H. Triyoso, R. I. Hegde, D. C. Gilmer, R. Garcia, D. Roan, M. L. Lovejoy, R. Rai, E.A. Hebert, H.‐H. Tseng, S.G.H. Anderson, B. E. White, P.J. Tobin,

Advancements in Semiconductor Devices and Circuit Design

We report here that Fermi pinning at the polysilicon/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. We show that this fundamental characteristic affects the observed polysilicon depletion. In Part I, the theoretical background is reviewed and the impact of the different gate stack regions are separated out by investigating the relative threshold voltage shifts of devices with Hf-based dielectrics. The effects of the interfacial bonding are examined in Part II.