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Simulation and expected performance analysis of multiple processor Z-buffer systems

1980; ACM SIGGRAPH; Volume: 14; Issue: 3 Linguagem: Inglês

10.1145/965105.807467

1558-4569

Frederic I. Parke,

Digital Image Processing Techniques

The results of expected performance analysis and simulation of three multiple processor Z-buffer architectures are presented. These architectures have been proposed as approaches to applying many processors, working in parallel, to the task of rapidly creating shaded raster images. These architectures are attractive since they offer potentially high performance, in terms of image update rate, at modest cost. All three approaches make use of multiple instances of identical processor modules. The analyses and simulations indicate that substantial gain is possible by applying multiple processors to the task. But, as more and more processors are added, additional gains in performance become smaller and smaller. This result suggests optimal system sizes. The performance of these architectures depends on the processors used, the number of processors, and certain characteristics of the image environments. Each architecture has its own performance characteristics and limitations.