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Early Soft Error Reliability Analysis on RISC-V

2022; Institute of Electrical and Electronics Engineers; Volume: 20; Issue: 9 Linguagem: Inglês

10.1109/tla.2022.9878169

1548-0992

Nicolas Lodéa, Willian Analdo Nunes, Vitor Balbinot Zanini, M. Sartori, Luciano Ost, Ney Calazans, Rafael Garibotti, César Marcon,

Real-Time Systems Scheduling

The adoption of RISC-V processors bloomed in recent years, mainly due to its open standard and free instruction set architecture. However, much remains to help software engineers deliver high-reliability and bug-free applications and systems based on RISC-V IP designs. This work proposes an early soft error reliability assessment of a RISC-V processor, extending the previously proposed SOFIA fault injection framework. Results from 850k fault injections show that choosing the compiler flag -O2 to optimize performance causes 96% more Hang failures than -O0. Software engineers must evaluate compilation parameters on a case-by-case basis to find the best balance between performance and reliability. This work helps software engineers develop fault-tolerant RISC-V-based systems and applications more efficiently.