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Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

2022; Association for Computing Machinery; Volume: 20; Issue: 2 Linguagem: Inglês

10.1145/3575861

1544-3973

Francesco Minervini, Oscar Palomar, Osman Ünsal, Enrico Reggiani, Josue V. Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto González, Jonnatan Mendoza, Ivan Vargas Valdivieso, César Alejandro Hernández, Joan Cabré, Lina Khoirunisya, Mustapha Bouhali, Julián Pavón, Francesc Moll, Mauro Olivieri, Mario Kovač, Mate Kovač, Leon Dragić, Mateo Valero, Adrián Cristal,

Interconnection Networks and Systems

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance Computing (HPC) application domain. In this article, 1 we present Vitruvius+, the vector processing acceleration engine that represents the core of vector instruction execution in the HPC challenge that comes within the EuroHPC initiative. It implements the RISC-V vector extension (RVV) 0.7.1 and can be easily connected to a scalar core using the Open Vector Interface standard. Vitruvius+ natively supports long vectors: 256 double precision floating-point elements in a single vector register. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File and functional units (one integer, one floating point). The vector instruction execution scheme is hybrid in-order/out-of-order and is supported by register renaming and arithmetic/memory instruction decoupling. On a stand-alone synthesis, Vitruvius+ reaches a maximum frequency of 1.4 GHz in typical conditions (TT/0.80V/25°C) using GlobalFoundries 22FDX FD-SOI. The silicon implementation has a total area of 1.3 mm 2 and maximum estimated power of ∼920 mW for one instance of Vitruvius+ equipped with eight vector lanes.