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Research on key technologies of multi-core DSP in smart substation redundancy network testing

2023; IOP Publishing; Volume: 2427; Issue: 1 Linguagem: Inglês

10.1088/1742-6596/2427/1/012046

1742-6596

Taonan Tang, Bolong Sun, Zhonglei Li, Minghua Yang, Shuwei Yi, Yibo Wang,

Embedded Systems and FPGA Design

Abstract Aiming at the network characteristics of a smart substation redundant network with complex communication messages, a large amount of interactive data, and high real-time performance, the test model of multiple submachines in a High-Availability Seamless Redundancy (HSR) loop network is analyzed. The requirements of packet types, size, and transmission speed are evaluated, and a hardware solution based on a multi-core Digital Signal Processor (DSP) and Parallel architecture FPGA is designed. The multi-core interaction strategy of DSP software and the multi-port high-speed communication method of FPGA are proposed, and the inter-core communication (IPC) interrupts and shared memory to achieve fast data migration between cores, based on the Serial RapidIO (SRIO) to complete high-speed message transmission. The throughput, delay, packet loss rate, and error frame detection functions are realized, tested, and verified, providing theoretical and practical support for the evaluation of redundant network performance of smart substations.