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Speed-Power Efficient Novel CMOS Unary-to-Ternary Encoder

2023; Taylor & Francis; Volume: 70; Issue: 6 Linguagem: Inglês

10.1080/03772063.2023.2264250

0974-780X

Aloke Saha, Prerona Sanyal, Deep Narayan Singh, Aastha Bharti, Dipankar Pal,

Advancements in Semiconductor Devices and Circuit Design

AbstractA new full-custom design of Unary-to-Ternary-Encoder (UTE) using standard Enhancement-Type-Metal–Oxide-Semiconductor-Field-Effect-Transistor reporting low-PDP (Power-Delay-Product) and low-area is presented. The inherent pass characteristic of the E-MOS-transistor is exploited here to develop the proposed Ternary-Encoder. Theoretical aspects along with the operation of proposed 9:2 and 27:3 UTE are discussed. The complete UTE is designed and optimized on 32 nm standard CMOS technology at 0.9 V supply-rail and 27°C. Ternary digits "0", "1" and "2" are represented with 0 V, 0.45 V and 0.9 V respectively. The proposed design is validated through extensive T-Spice front-end transient simulations with all possible test patterns. The layout of the proposed design is completed on 32 nm Single-Poly-Double-Metal (SPDM) CMOS--Technology. After DRC and LVS post-layout simulation with extracted parasitic and 1 fF load, is carried out. The valuated performance of the 9:2 UTE is next compared with a recent candidate design to this end, from open literature to benchmark. The Power-Delay-Product (PDP) of proposed UTE is measured by applying ±10% supply variation from nominal on slow, typical and fast MOSFET at −40°C, 27°C and 85°C. Finally, the speed-power characteristic of the proposed 9:2 UTE is explored under different load conditions from 1 to 10 fF.Keywords: E-MOS pass characteristic; Encoding scheme; PDP (Power delay product); PVT (Process-voltage-temperature) analyses; Transient analyses; Ternary system Disclosure statementNo potential conflict of interest was reported by the author(s).Additional informationNotes on contributorsAloke SahaAloke Saha (M'15) received Btech degree in EIE from Kalyani University, India in 2003, ME degree in ECE (Instr. & Control) and PhD in Engineering from BIT Mesra, India in 2006 and 2015 respectively. He was associated with ECE Department of BIT Mesra as a Lecturer from 2006 to 2009. Presently he is an assistant professor of electronics and communication engineering (ECE) at Dr B. C. Roy Engineering College, Durgapur, India. Dr Saha is a reviewer for several SCI/ESCI/Scopus Indexed Technical Journals and has published a number of good-quality research papers. His area of interest includes cut-in age efficient digital computing, ternary and/or double base system development, encryption/decryption strategy, bio-medical signal processing, scalable architecture with adaptive control, floating point circuit/system etc. Email: saha81@gmail.comPrerona SanyalPrerona Sanyal was born in Asansol, India in the year of July 1991. Ms P. Sanyal completed her diploma in electronics and telecommunication engineering from "The New Horizon Institute of Technology", Durgapur, India in the year 2015. She received her Btech in electronics and communication engineering and Mtech in modern communication engineering (ECE) from Dr B. C. Roy Engineering College, Durgapur, India in the years 2018 and 2020 respectively. Her current research interest includes data security, circuit-optimization, ternary system etc. Email: prernasanyal@gmail.comDeep Narayan SinghDeep Narayan Singh was born in Varanasi, India in the year of October 1994. Mr Deep Narayan Singh received her diploma in electrical and electronics engineering from "Xavier Institute of Polytechnic and Technology", Ranchi and pursuing a Btech in electronics and communication engineering from Dr B. C. Roy Engineering College, Durgapur, India in the year of 2019 and 2022 respectively. His current research interest includes VLSI system optimization, parallel processing, low-power system design etc. Email: deepxipt@gmail.comAastha BhartiAastha Bharti was born in Deoghar, Jharkhand, India in the year of March 2001. Ms A. Bharti is pursuing her Btech in electronics and communication engineering from Dr B. C. Roy Engineering College, Durgapur. Her current research interest includes microelectronics circuits/systems, signal processing, number systems. Email: aasthabharti1003@gmail.comDipankar PalDipankar Pal (M'1999–SM'2008) was born in Chandannagar, India, in 1961. He received his Btech degree in electrical engineering from the Indian Institute of Technology, Delhi, India, in 1984 and his PhD. degree in electronics and telecommunication engineering from Jadavpur University, Calcutta, India, in 1997. In 2002, he was a Royal Society Visiting Fellow at the University College London (UCL), London, U.K. From 2003 to 2005, he was an EPSRC Research Fellow at the University of Bath, Bath, U.K. From 2007 to 2008 he was a Visiting Fellow at UCL. He was also a professor of microelectronics at the Birla Institute of Technology (BIT), Mesra, India, where he headed the microelectronics and VLSI research group within the department of electronics and communication engineering. From 2011 to 2014 he served as the Director of the North Eastern Regional Institute of Science & Technology (NERIST), a deemed university under MHRD, Government of India. Currently, he is a professor of microelectronics in the department of electrical & electronics engineering at BITS Pilani, K. K. Birla Goa-Campus, India. He has published over 60 articles in peer-reviewed journals and international conference proceedings. His research area includes microelectronics, digital and analog circuits and systems, and analog ASIC. Dr Pal is a Fellow of the Institution of Engineers (India). Corresponding author. Email: dipankarp@goa.bits-pilani.ac.in